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/**************************************************************************/
/*!
Wait VSYNC signal.
*/
/**************************************************************************/
void Display_WaitVSYNC(void)
{
/* reload shadow registers on vertical blanking period */
LTDC->SRCR = LTDC_SRCR_VBR;
/* wait for next frame */
while ((LTDC->CDSR & LTDC_CDSR_VSYNCS) == 0);
}

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	/* Timing parameters for all Video modes
* Set Timing parameters of LTDC depending on its chosen orientation
*/
/* The following values are same for portrait and landscape orientations */
if(Orientation == LCD_ORIENTATION_PORTRAIT)
{
VSA = OTM8009A_480X800_VSYNC; /* 1 */
VBP = OTM8009A_480X800_VBP; /* 15 */
VFP = OTM8009A_480X800_VFP; /* 16 */
HSA = OTM8009A_480X800_HSYNC; /* 2 */
HBP = OTM8009A_480X800_HBP; /* 34 */
HFP = OTM8009A_480X800_HFP; /* 34 */
}
else
{
/* lcd_orientation == LCD_ORIENTATION_LANDSCAPE */
VSA = OTM8009A_800X480_VSYNC; /* 1 */
VBP = VBP_OFS + OTM8009A_800X480_VBP; /* 15(+480) */
VFP = OTM8009A_800X480_VFP; /* 16 */
HSA = OTM8009A_800X480_HSYNC; /* 2 */
HBP = OTM8009A_800X480_HBP; /* 34 */
HFP = OTM8009A_800X480_HFP; /* 34 */
}




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arm-none-eabi-gcc (Arm GNU Toolchain 13.2.rel1 (Build arm-13.7)) 13.2.1 20231009
Copyright (C) 2023 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Built Object Informations:
=== Total Binary Size ===
text data bss dec hex filename
0 479156 0 479156 74fb4 main.hex
=== Verbose ELF Size ===
text data bss dec hex filename
477416 1740 39668 518824 7eaa8 main.elf
main.elf :
section size addr
.text 0x747fc 0x8000000
.ctors 0x0 0x80747fc
.dtors 0x0 0x80747fc
.eh_frame 0x54 0x80747fc
.ARM.exidx 0x98 0x8074850
.data 0x6cc 0x20000000
.bss 0x18a8 0x200006d0
.heap 0x0 0x20001f78
.ram2 0x0 0x20040000
.stack 0x0 0x20040000
.ram3 0x824c 0x20050000
.bkpram 0x0 0x40036400
.qspirom 0x0 0x90000000
.comment 0x44 0x0
.debug_frame 0x1e88 0x0
.ARM.attributes 0x38 0x0
.debug_line_str 0x1f2 0x0
Total 0x80b9e

13.3Rel1(¿·¤·¤¤¤Û¤¦)
arm-none-eabi-gcc (Arm GNU Toolchain 13.3.Rel1 (Build arm-13.24)) 13.3.1 20240614
Copyright (C) 2023 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Built Object Informations:
=== Total Binary Size ===
text data bss dec hex filename
0 478396 0 478396 74cbc main.hex
=== Verbose ELF Size ===
text data bss dec hex filename
476624 1772 39668 518064 7e7b0 main.elf
main.elf :
section size addr
.text 0x744e4 0x8000000
.ctors 0x0 0x80744e4
.dtors 0x0 0x80744e4
.eh_frame 0x54 0x80744e4
.ARM.exidx 0x98 0x8074538
.data 0x6ec 0x20000000
.bss 0x18a8 0x200006f0
.heap 0x0 0x20001f98
.ram2 0x0 0x20040000
.stack 0x0 0x20040000
.ram3 0x824c 0x20050000
.bkpram 0x0 0x40036400
.qspirom 0x0 0x90000000
.comment 0x45 0x0
.debug_frame 0x1d98 0x0
.ARM.attributes 0x38 0x0
.debug_line_str 0x1f2 0x0
Total 0x807b7

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Built Object Informations:
=== Total Binary Size ===
text data bss dec hex filename
0 478260 0 478260 74c34 main.hex
=== Verbose ELF Size ===
text data bss dec hex filename
476488 1772 39668 517928 7e728 main.elf

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 Built Object Informations:
=== Total Binary Size ===
text data bss dec hex filename
0 473372 0 473372 7391c main.hex
=== Verbose ELF Size ===
text data bss dec hex filename
471608 1764 39672 513044 7d414 main.elf


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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink-v2.cfg -c "transport select hla_swd" -f target/lpc81x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.12.0+dev-00682-gefe902219 (2024-08-12-08:52)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
DEPRECATED! use 'gdb target_description', not 'gdb_target_description'
Info : clock speed 1000 kHz
Info : STLINK V2J45S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 2.905861
Info : [lpc81x.cpu] Cortex-M0+ r0p0 processor detected
Info : [lpc81x.cpu] target has 4 breakpoints, 2 watchpoints
Info : [lpc81x.cpu] Examination succeed
Info : [lpc81x.cpu] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
[lpc81x.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff0008 msp: 0x10000ffc
Info : wrote 3072 bytes from file main.elf in 1.093837s (2.743 KiB/s)
Info : verified 3072 bytes in 0.055933s (53.636 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:01

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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink-dap.cfg -c "transport select dapdirect_swd" -f target/lpc81x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.12.0+dev-00682-gefe902219 (2024-08-12-08:52)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'gdb target_description', not 'gdb_target_description'
Info : STLINK V2J45S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 2.882555
Info : Unable to match requested speed 1000 kHz, using 950 kHz
Info : Unable to match requested speed 1000 kHz, using 950 kHz
Info : clock speed 950 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x0bc11477
Info : [lpc81x.cpu] Cortex-M0+ r0p0 processor detected
Info : [lpc81x.cpu] target has 4 breakpoints, 2 watchpoints
Info : [lpc81x.cpu] Examination succeed
Info : [lpc81x.cpu] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
[lpc81x.cpu] halted due to breakpoint, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff0008 msp: 0x10000ffc
Info : wrote 3072 bytes from file main.elf in 1.219387s (2.460 KiB/s)
Info : verified 3072 bytes in 0.063133s (47.519 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:03



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# SPDX-License-Identifier: GPL-2.0-or-later

# script for stm32u0x family
#
# stm32u0 devices support SWD transports only.
#

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32u0x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 6kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1800
}

#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# SWD IDCODE (single drop, arm)
set _CPUTAPID 0x0bc11477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff6800 0 0 0 $_TARGETNAME

# reasonable default
adapter speed 2000

adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
# Enable DBGMCU clock
# RCC_DBGCFGR |= DBGEN
mmw 0x40021050 0x00000001 0

# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
mmw 0x40015804 0x0000000C 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0x40015808 0x00001800 0
}

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# script for stm32u0x with flash programming
# Nemuisan's Special


source [find target/stm32u0x.cfg]
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

proc mt_flash {IMGFILE} {
flash write_image erase $IMGFILE
verify_image $IMGFILE
reset run
shutdown
}

proc mt_flash_bin {IMGFILE OFFSET} {
flash write_image erase $IMGFILE $OFFSET bin
verify_image $IMGFILE $OFFSET
reset run
shutdown
}

proc mt_flash_hex {IMGFILE} {
flash write_image erase $IMGFILE 0 ihex
verify_image $IMGFILE 0
reset run
shutdown
}

proc eraser {} {
stm32g0x mass_erase 0
flash erase_check 0
shutdown
}

#debug_level 3
#reset_config srst_only srst_nogate connect_assert_srst
reset_config none
adapter speed 500
gdb_target_description enable
init
reset init


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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink-dap.cfg -c "transport select dapdirect_swd" -f target/stm32u0x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.12.0+dev-00658-g6554d176e (2024-07-21-10:18)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
dapdirect_swd
DEPRECATED! use 'gdb target_description', not 'gdb_target_description'
Info : STLINK V2J45M30 (API v2) VID:PID 0483:3752
Info : Target voltage: 3.236554
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : clock speed 480 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : [stm32u0x.cpu] Cortex-M0+ r0p1 processor detected
Info : [stm32u0x.cpu] target has 4 breakpoints, 2 watchpoints
Info : [stm32u0x.cpu] Examination succeed
Info : [stm32u0x.cpu] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
[stm32u0x.cpu] halted due to breakpoint, current mode: Thread
xPSR: 0xf1000000 pc: 0x08002b30 msp: 0x2000a000
Info : device idcode = 0x10006489 (STM32U07/U08xx - Rev A : 0x1000)
Info : RDP level 0 (0xAA)
Info : flash size = 256 KiB
Info : flash mode : single-bank
Info : Padding image section 1 at 0x08008004 with 4 bytes (bank write end alignment)
Warn : Adding extra erase range, 0x08008008 .. 0x080087ff
Info : wrote 32776 bytes from file main.elf in 1.595168s (20.065 KiB/s)
Info : verified 32772 bytes in 0.780823s (40.987 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:03



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/* STM32U0 DeviceID & Revision Detection */
char mcurev;
__HAL_RCC_DBGMCU_CLK_ENABLE(); // <- ¤³¤ì
uint16_t revid = HAL_GetREVID();
uint16_t devid = 0x0FFF & HAL_GetDEVID();
if (revid == 0x1001) mcurev = 'Z';
else /* 0x1000 */ mcurev = 'A';
printf("STM32U0xx DevID 0x%04x Rev.%c¥n",devid,mcurev);
printf("STM32U0xx UID 0x%08lx%08lx%08lx¥n",HAL_GetUIDw2(),HAL_GetUIDw1(),HAL_GetUIDw0());
printf("¥n");
#endif


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#============================================================================
# Define programs and commands.
SHELL = sh
CC = avr-gcc
OBJCOPY = avr-objcopy
OBJDUMP = avr-objdump
SIZE = avr-size
NM = avr-nm
AVRDUDE = avrdude
REMOVE = rm -f
REMOVEDIR = rm -rf
COPY = cp
WINSHELL = cmd
# Detect GCC version
GCCVERSION:= $(shell $(CC) -dumpversion)
dot:=.
empty:=
space:= $(empty) $(empty)
GCCVERSION:= $(subst $(dot),$(space), $(GCCVERSION))
GCCMAJOR:= $(word 1, $(GCCVERSION))
GCCMINOR:= $(word 2, $(GCCVERSION))


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# If GCC 14+ Add -mrodata-in-ram to get backward compatibility on AVR uC
ifeq (1,$(shell expr $(GCCMAJOR) ¥>= 14))
ifneq ($(MCU),avr32da28)
ifeq ($(USE_SECTOR_MIRROR),SECTOR_MIRRORED)
CFLAGS += -mrodata-in-ram
endif
endif
endif

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Compiling: src/xprintf_avr.c
avr-gcc -c -mmcu=avr128da48 -std=gnu99 -g -gdwarf-2 -Os -mrelax -mcall-prologues -fno-strict-aliasing -funsigned-char -funsigned-bitfields -ffunction-sections -fdata-sections -fno-common -fanalyzer -fno-split-wide-types -fno-tree-scev-cprop -fpack-struct -fshort-enums -Wall -Wstrict-prototypes --param=min-pagesize=0 -Wa,-adhlns=src/xprintf_avr.lst -DCURIOSITY_NANO -DMPU_SUBMODEL=¥"avr128da48¥" -DAPP_VERSION=¥"W.I.P.¥" -DF_CPU=24000000UL -DSECTOR_SEL=UL -I. -I ./inc -I ./lib/ff -MD src/xprintf_avr.c -o src/xprintf_avr.o
src/xprintf_avr.c: In function 'xvprintf':
src/xprintf_avr.c:131:27: warning: 'va_arg' expected 'char *' but received 'long unsigned int' for variadic argument 1 of 'arp' [CWE-686] [-Wanalyzer-va-arg-type-mismatch]
131 | p = va_arg(arp, char*);
| ^
'put_dump': events 1-2
|
| 247 | void put_dump (
| | ^~~~~~~~
| | |
| | (1) entry to 'put_dump'
|......
| 260 | xprintf(PFSTR("%08lX "), addr); /* address */
| | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| | |
| | (2) calling 'xprintf' from 'put_dump' with 1 variadic argument
|
+--> 'xprintf': events 3-4
|
| 187 | void xprintf ( /* Put a formatted string to the default device */
| | ^~~~~~~
| | |
| | (3) entry to 'xprintf'
|......
| 196 | xvprintf(fmt, arp);
| | ~~~~~~~~~~~~~~~~~~
| | |
| | (4) calling 'xvprintf' from 'xprintf'
|
+--> 'xvprintf': events 5-8
|
| 96 | void xvprintf (
| | ^~~~~~~~
| | |
| | (5) entry to 'xvprintf'
|......
| 108 | if (!c) break; /* End of format? */
| | ~
| | |
| | (6) following 'false' branch (when '__result != 0')...
| 109 | if (c != '%') { /* Pass through it if not a % sequense */
| | ~
| | |
| | (7) ...to here
| | (8) following 'false' branch (when '__result == 37')...
|
'xvprintf': event 9
|
| 113 | c = PGM_READ_BYTE(fmt++); /* Get first char of the sequense */
src/xprintf_avr.c:113:21: note: in expansion of macro 'PGM_READ_BYTE'
| 113 | c = PGM_READ_BYTE(fmt++); /* Get first char of the sequense */
| | ^~~~~~~~~~~~~
|
'xvprintf': event 10
|
| 114 | if (c == '0') { /* Flag: '0' padded */
| | ^
| | |
| | (10) following 'true' branch (when '__result == 48')...
|
'xvprintf': event 11
|
| 115 | f = 1; c = PGM_READ_BYTE(fmt++);
src/xprintf_avr.c:115:36: note: in expansion of macro 'PGM_READ_BYTE'
| 115 | f = 1; c = PGM_READ_BYTE(fmt++);
| | ^~~~~~~~~~~~~
|
'xvprintf': events 12-15
|
| 121 | for (w = 0; c >= '0' && c <= '9'; c = PGM_READ_BYTE(fmt++)) /* Minimum width */
| | ~~~~~~~~~^~~~~~~~~~~
| | |
| | (12) following 'false' branch...
| 122 | w = w * 10 + c - '0';
| 123 | if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
| | ~
| | |
| | (13) ...to here
|......
| 126 | if (!c) break; /* End of format? */
| | ~
| | |
| | (14) following 'false' branch (when 'c != 0')...
|......
| 129 | switch (d) { /* Type is... */
| | ~~~~~~
| | |
| | (15) ...to here
|
'xvprintf': event 16
|
| 131 | p = va_arg(arp, char*);
| | ^
| | |
| | (16) 'va_arg' expected 'char *' but received 'long unsigned int' for variadic argument 1 of 'arp'
|

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f_read¤Î·ë¹ç´Ø¿ôSD_read()¤Ï¤³¤ó¤Ê´¶¤¸¤Ç¤¹¡£

DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_OK;
uint32_t timer = SysTick->VAL + SD_DATATIMEOUT;

/* first ensure the SDCard is ready for a new operation */
while((SD_GetCardState() == SD_TRANSFER_BUSY))
{
if(timer < SysTick->VAL)
return RES_NOTRDY;
}

#if defined(SD_DMA_MODE) && !defined(SD_POLLING_MODE)

if((uintptr_t)buff & 0x3) /* Check 4Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count ; secNum++){

if(SD_ReadBlocks_DMA((uint32_t*)dmabuf, (uint32_t)(sector+secNum), 1)!= MSD_OK)
{
MSG_PRINTF("Read error on unaligned buffer¥n");
res = RES_ERROR;
}

memcpy(buff+secNum*SECTOR_SIZE, dmabuf, SECTOR_SIZE);
}
} else {
/* Aligned Buffer Address Case (Faster) */
if(SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Read error on DMA¥n");
res = RES_ERROR;
}
}
#else
if(SD_ReadBlocks((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Read error on polling¥n");
res = RES_ERROR;
}
#endif
return res;
}


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DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_ERROR;
uint32_t timer;


#if defined(SD_DMA_MODE) && !defined(SD_POLLING_MODE)
if((uintptr_t)buff & 0x3) /* Check 4Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count; secNum++){

memcpy(dmabuf, buff+(SECTOR_SIZE*secNum), SECTOR_SIZE);

if(SD_WriteBlocks_DMA((uint32_t*)dmabuf, (uint32_t)(sector+secNum), 1) != MSD_OK)
{
MSG_PRINTF("Write error on unaligned buffer¥n");
res = RES_ERROR;
}
}
} else {
if(SD_WriteBlocks_DMA((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Write error on DMA¥n");
res = RES_ERROR;
}
}
#else
if(SD_WriteBlocks((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Write error on polling¥n");
res = RES_ERROR;
}

#endif

/* ensure the SDCard is ready for a next operation */
timer = SysTick->VAL + SD_DATATIMEOUT;
res = RES_ERROR; /* Timeout */
/* block until SDIO IP is ready or a timeout occur */
while(timer > SysTick->VAL)
{
if(SD_GetCardState() == SD_TRANSFER_OK)
{
res = RES_OK;
break;
}
}

return res;
}

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²¼µ­¥Ç¥£¥ì¥¯¥È¥ê¤Î¥Õ¥¡¥¤¥ë¤ò»²¾È¤·¤Æ¤¯¤À¤µ¤¤¡£
./lib/ff/sdmmc_stm32h5.c
./lib/ff/sdmmc_stm32h5.h


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STM32H5¤ò»È¤Ã¤Æ¤ß¤ë5 -ÉáÄ̤ÎSPI¤òDMA¤È¸ò¤¨¤Æ»È¤¦-

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½©·î¤µ¤ó¤è¤êNUCLEO-H563ZIÈÎÇ䳫»Ï¤Ç¤¹¡ª¡ª
20240516ÄÉ:



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./lib/display/mcu_depend/src/display_if_basis.c¤ò²òÀ⤷¤Æ¤¤¤­¤Þ¤¹¡£
./lib/display/mcu_depend/inc/display_if_basis.h¤â»²¾È¤Î¤³¤È¡£

Display_IoInit_If()Æâ¤Ç¥Ï¡¼¥É¥¦¥¨¥¢SPI¤«¤éDMA¤ÎÀßÄê¤Þ¤Ç¤ä¤Ã¤Á¤ã¤Ã¤Æ
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	GPIO_InitTypeDef GPIO_InitStructure = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};

/* Enable CTRL line GPIO settings */
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_RES);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_CS);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_DC);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SCK);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDI);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDO);

GPIO_InitStructure.Pin = CTRL_RES;
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStructure.Alternate = 0;
HAL_GPIO_Init(DISPLAY_PORT_RES, &GPIO_InitStructure);

GPIO_InitStructure.Pin = CTRL_CS;
HAL_GPIO_Init(DISPLAY_PORT_CS, &GPIO_InitStructure);
GPIO_InitStructure.Pin = CTRL_DC;
HAL_GPIO_Init(DISPLAY_PORT_DC, &GPIO_InitStructure);

/* Set peripheral clock */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
for(;;){
__NOP();
}
}
DISPLAY_PERIF_CLK(ENABLE);

/* Connect SPI pins to aletenate function */
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;

/* SPI SCK pin configuration */
GPIO_InitStructure.Pin = CTRL_SCK;
GPIO_InitStructure.Alternate = SRC_SCK;
HAL_GPIO_Init(DISPLAY_PORT_SCK, &GPIO_InitStructure);

/* SPI MOSI pin configuration */
GPIO_InitStructure.Pin = CTRL_SDI;
GPIO_InitStructure.Alternate = SRC_SDI;
HAL_GPIO_Init(DISPLAY_PORT_SDI, &GPIO_InitStructure);

/* SPI MISO pin configuration */
GPIO_InitStructure.Pin = CTRL_SDO;
GPIO_InitStructure.Alternate = SRC_SDO;
HAL_GPIO_Init(DISPLAY_PORT_SDO, &GPIO_InitStructure);

SCK,MOSI,MISO¤ÏAlternateFunction¤È¤·¤Æ¡¢RESET¡¦CS¡¦DC¤ÏGPIO¤È¤·¤Æ
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	/* SPI configuration */
SpiHandle.Instance = LCD_SPI;
SpiHandle.Init.Mode = SPI_MODE_MASTER;
SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT;
SpiHandle.Init.CLKPolarity = SPI_POLARITY_HIGH;
SpiHandle.Init.CLKPhase = SPI_PHASE_2EDGE;
SpiHandle.Init.NSS = SPI_NSS_SOFT;
SpiHandle.Init.BaudRatePrescaler = SPI_BaudPrescale;
SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
SpiHandle.Init.TIMode = SPI_TIMODE_DISABLE;
SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
SpiHandle.Init.CRCPolynomial = 0x7;
SpiHandle.Init.CRCLength = SPI_CRC_LENGTH_8BIT;
SpiHandle.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
SpiHandle.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
SpiHandle.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
SpiHandle.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
SpiHandle.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
SpiHandle.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
SpiHandle.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; /* avoid glitch */
SpiHandle.Init.IOSwap = SPI_IO_SWAP_DISABLE;
SpiHandle.Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY;
SpiHandle.Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH;
if(HAL_SPI_Init(&SpiHandle) != HAL_OK)
{
/* Capture error */
while (1);
}

/* Enable SPI module */
LCD_SPI->CR1 |= SPI_CR1_SPE;
LCD_SPI->CR1 |= SPI_CR1_CSTART;

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SpiHandle.Init.BaudRatePrescaler 		= SPI_BaudPrescale;

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#define SPI_BaudPrescale	SPI_BAUDRATEPRESCALER_4 /* PLL1Q CLK 100MHz/4 = 25MHz */

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ST7789V2¤ÎSCL¤Î¥¯¥í¥Ã¥¯ºÇÂçÃͤÁ¤ã¤ó¤ÈÄ´¤Ù¤¿¤é¤Ê¤ó¤È60MHz¤Ç¤·¤¿¡ª¡ª¡ª
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	/* DMA controller clock enable */
__HAL_RCC_GPDMA1_CLK_ENABLE();

/* DMA interrupt init */
/* SPILCD_DMA_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SPILCD_DMA_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(SPILCD_DMA_IRQn);

/* Configure DMA request LcdDmaHandle */
LcdDmaHandle.Instance = SPILCD_DMA_CHANNEL;
LcdDmaHandle.Init.Request = SPILCD_DMA_REQEST;
LcdDmaHandle.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
LcdDmaHandle.Init.Direction = DMA_MEMORY_TO_PERIPH;
LcdDmaHandle.Init.SrcInc = DMA_SINC_INCREMENTED;
LcdDmaHandle.Init.DestInc = DMA_DINC_FIXED;
LcdDmaHandle.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
LcdDmaHandle.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
LcdDmaHandle.Init.Priority = DMA_LOW_PRIORITY_HIGH_WEIGHT;
LcdDmaHandle.Init.SrcBurstLength = 1;
LcdDmaHandle.Init.DestBurstLength = 1;
LcdDmaHandle.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
LcdDmaHandle.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
LcdDmaHandle.Init.Mode = DMA_NORMAL;
if (HAL_DMA_Init(&LcdDmaHandle) != HAL_OK)
{
for(;;){
__NOP();
}
}
__HAL_LINKDMA(&SpiHandle,hdmatx,LcdDmaHandle);

if (HAL_DMA_ConfigChannelAttributes(&LcdDmaHandle, DMA_CHANNEL_NPRIV) != HAL_OK)
{
for(;;){
__NOP();
}
}

/* SPI interrupt init */
/* SPILCD_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SPILCD_IRQn, 3, 1);
HAL_NVIC_EnableIRQ(SPILCD_IRQn);

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    LcdDmaHandle.Init.Direction 			= DMA_MEMORY_TO_PERIPH;
LcdDmaHandle.Init.SrcInc = DMA_SINC_INCREMENTED;
LcdDmaHandle.Init.DestInc = DMA_DINC_FIXED;
LcdDmaHandle.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
LcdDmaHandle.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;

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#define SPIx_TDR8			*(__IO uint8_t *) ((uint32_t)LCD_SPI+0x20)
#define SPIx_RDR8 *(__IO uint8_t *) ((uint32_t)LCD_SPI+0x30)


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inline void SendSPI(uint8_t dat)
{
/* Send byte through the SPI peripheral */
SPIx_TDR8 = dat;

/* Wait to receive a byte */
while (!(LCD_SPI->SR & (SPI_FLAG_RXP)));

/* Drain Rx FIFO */
SPIx_RDR8;
}

inline void SendSPI16(uint16_t dat)
{
SendSPI((uint8_t)(dat>>8));

SendSPI((uint8_t)dat);
}

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¤µ¤é¤ËST7789V2¸þ¤±¤Ë¤Ï¾åµ­´Ø¿ô¤òÍøÍѤ·¤ÆCMD,DATA,GRAM½ñ¤­¹þ¤ßÍѤËÙϤ¨¤Þ¤¹¡£
/**************************************************************************/
/*!
Write LCD Command.
*/
/**************************************************************************/
inline void ST7789V2_wr_cmd(uint8_t cmd)
{
ST7789V2_DC_CLR(); /* DC=L */
DISPLAY_ASSART_CS(); /* CS=L */

SendSPI(cmd);

DISPLAY_NEGATE_CS(); /* CS=H */
ST7789V2_DC_SET(); /* DC=H */
}

/**************************************************************************/
/*!
Write LCD Data and GRAM.
*/
/**************************************************************************/
inline void ST7789V2_wr_dat(uint8_t dat)
{
DISPLAY_ASSART_CS(); /* CS=L */

SendSPI(dat);

DISPLAY_NEGATE_CS(); /* CS=H */
}

/**************************************************************************/
/*!
Write LCD GRAM.
*/
/**************************************************************************/
inline void ST7789V2_wr_gram(uint16_t gram)
{
DISPLAY_ASSART_CS(); /* CS=L */

SendSPI16(gram);

DISPLAY_NEGATE_CS(); /* CS=H */
}



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/* DMA IRQ Handler */
void SPILCD_DMA_HANDLER(void)
{
HAL_DMA_IRQHandler(&LcdDmaHandle);
}
/* SPI IRQ Handler */
void SPILCD_IRQHandler(void)
{
HAL_SPI_IRQHandler(&SpiHandle);
}


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/* SPI-DMA IRQ Callback */
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
if(hspi->Instance == LCD_SPI){
wTransferState = TRANSFER_COMPLETE;
}
}

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/* DMA transaction */
void lcd_dma_transfer(const uint8_t *buff,unsigned int count)
{
/* Disable SPI to change register */
LCD_SPI->CR1 &= ~(SPI_CR1_SPE);

/* Start DMA */
if (HAL_SPI_Transmit_DMA(&SpiHandle, buff, count) != HAL_OK)
{
for(;;){
__NOP();
}
}

/* Wait transfer complete */
while (wTransferState == TRANSFER_WAIT) {};

/* Restore transfer state */
wTransferState = TRANSFER_WAIT;

/* Restore nomal transfer settings */
LCD_SPI->CR2 = 0; /* Restore TSIZE */
LCD_SPI->CFG2 &= ~(SPI_CFG2_COMM_Msk); /* Restore FULL duplex mode */
LCD_SPI->CR1 |= SPI_CR1_SPE; /* Re-enable SPI module */
LCD_SPI->CR1 |= SPI_CR1_CSTART; /* Re-start SPI Trasfer ready */
}

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/* Restore nomal transfer settings */
LCD_SPI->CR2 = 0; /* Restore TSIZE */
LCD_SPI->CFG2 &= ~(SPI_CFG2_COMM_Msk); /* Restore FULL duplex mode */
LCD_SPI->CR1 |= SPI_CR1_SPE; /* Re-enable SPI module */
LCD_SPI->CR1 |= SPI_CR1_CSTART; /* Re-start SPI Trasfer ready */

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