OpenOCD小ネタ22 -STM32F7系CFG変更の件-
まだ6月ですがもう梅雨が終わりそうなくらい暑いですね〜
子供の頃の季節感覚だと6月に梅雨が終わり7月から夏!
て感覚なので実際の季節がそれに近くなってるのかも…
さて、OpenOCDのSTM32F7系向けのcfgファイルが更新されていますので
お知らせします。
内容はリセット時のクロック設定を内部高速クロックに変えて、さらにPLLを
経てコアクロック周波数160MHzにブーストしたものが反映されております。
スクリプトはオリジナルは…
$_TARGETNAME configure -event reset-init {
# Configure PLL to boost clock to HSI x 10 (160 MHz)
mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
sleep 10 ;# Wait for PLL to lock
mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
# Boost SWD frequency
# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
# suffers from DAP WAITs
if {[using_jtag]} {
[[target current] cget -dap] memaccess 16
} {
adapter_khz 8000
}
}
$_TARGETNAME configure -event reset-start {
# Reduce speed since CPU speed will slow down to 16MHz with the reset
adapter_khz 2000
}
となっていますがねむいさん提供のOpenOCDバイナリはオリジナルから若干違います。
$_TARGETNAME configure -event reset-init {
mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
# Configure PLL to boost clock to HSI x 4 (64 MHz)
mww 0x40023804 0x03001008 ;# RCC_PLLCFGR 16 Mhz / 8(M) * 64(N) / 2(P)
mmw 0x40023800 0x01000001 0 ;# RCC_CR |= PLLON | HSION
sleep 10 ;# Wait for PLL to lock
mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
# Boost JTAG frequency
adapter_khz 4000
}
コアクロックを上げた後クロックを上げていますが安全のためオリジナルと違って
4000kHzまでとしております(JLINKがこの周波数以上ではなぜか不安定)。
いずれにせよ使用感は変更前とまったく変わらない感覚ですので皆さま安心して
お使いいただけると思います!
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