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/**************************************************************************/
/*!
Wait VSYNC signal.
*/
/**************************************************************************/
void Display_WaitVSYNC(void)
{
/* reload shadow registers on vertical blanking period */
LTDC->SRCR = LTDC_SRCR_VBR;
/* wait for next frame */
while ((LTDC->CDSR & LTDC_CDSR_VSYNCS) == 0);
}

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	/* Timing parameters for all Video modes
* Set Timing parameters of LTDC depending on its chosen orientation
*/
/* The following values are same for portrait and landscape orientations */
if(Orientation == LCD_ORIENTATION_PORTRAIT)
{
VSA = OTM8009A_480X800_VSYNC; /* 1 */
VBP = OTM8009A_480X800_VBP; /* 15 */
VFP = OTM8009A_480X800_VFP; /* 16 */
HSA = OTM8009A_480X800_HSYNC; /* 2 */
HBP = OTM8009A_480X800_HBP; /* 34 */
HFP = OTM8009A_480X800_HFP; /* 34 */
}
else
{
/* lcd_orientation == LCD_ORIENTATION_LANDSCAPE */
VSA = OTM8009A_800X480_VSYNC; /* 1 */
VBP = VBP_OFS + OTM8009A_800X480_VBP; /* 15(+480) */
VFP = OTM8009A_800X480_VFP; /* 16 */
HSA = OTM8009A_800X480_HSYNC; /* 2 */
HBP = OTM8009A_800X480_HBP; /* 34 */
HFP = OTM8009A_800X480_HFP; /* 34 */
}




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# SPDX-License-Identifier: GPL-2.0-or-later

# script for stm32u0x family
#
# stm32u0 devices support SWD transports only.
#

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32u0x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 6kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1800
}

#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# SWD IDCODE (single drop, arm)
set _CPUTAPID 0x0bc11477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff6800 0 0 0 $_TARGETNAME

# reasonable default
adapter speed 2000

adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
# Enable DBGMCU clock
# RCC_DBGCFGR |= DBGEN
mmw 0x40021050 0x00000001 0

# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
mmw 0x40015804 0x0000000C 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0x40015808 0x00001800 0
}

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# script for stm32u0x with flash programming
# Nemuisan's Special


source [find target/stm32u0x.cfg]
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

proc mt_flash {IMGFILE} {
flash write_image erase $IMGFILE
verify_image $IMGFILE
reset run
shutdown
}

proc mt_flash_bin {IMGFILE OFFSET} {
flash write_image erase $IMGFILE $OFFSET bin
verify_image $IMGFILE $OFFSET
reset run
shutdown
}

proc mt_flash_hex {IMGFILE} {
flash write_image erase $IMGFILE 0 ihex
verify_image $IMGFILE 0
reset run
shutdown
}

proc eraser {} {
stm32g0x mass_erase 0
flash erase_check 0
shutdown
}

#debug_level 3
#reset_config srst_only srst_nogate connect_assert_srst
reset_config none
adapter speed 500
gdb_target_description enable
init
reset init


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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink-dap.cfg -c "transport select dapdirect_swd" -f target/stm32u0x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.12.0+dev-00658-g6554d176e (2024-07-21-10:18)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
dapdirect_swd
DEPRECATED! use 'gdb target_description', not 'gdb_target_description'
Info : STLINK V2J45M30 (API v2) VID:PID 0483:3752
Info : Target voltage: 3.236554
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : clock speed 480 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : [stm32u0x.cpu] Cortex-M0+ r0p1 processor detected
Info : [stm32u0x.cpu] target has 4 breakpoints, 2 watchpoints
Info : [stm32u0x.cpu] Examination succeed
Info : [stm32u0x.cpu] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
[stm32u0x.cpu] halted due to breakpoint, current mode: Thread
xPSR: 0xf1000000 pc: 0x08002b30 msp: 0x2000a000
Info : device idcode = 0x10006489 (STM32U07/U08xx - Rev A : 0x1000)
Info : RDP level 0 (0xAA)
Info : flash size = 256 KiB
Info : flash mode : single-bank
Info : Padding image section 1 at 0x08008004 with 4 bytes (bank write end alignment)
Warn : Adding extra erase range, 0x08008008 .. 0x080087ff
Info : wrote 32776 bytes from file main.elf in 1.595168s (20.065 KiB/s)
Info : verified 32772 bytes in 0.780823s (40.987 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:03



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#if defined(USE_STM32U083RC_NUCLEO)
/* STM32U0 DeviceID & Revision Detection */
char mcurev;
__HAL_RCC_DBGMCU_CLK_ENABLE(); // <- ¤³¤ì
uint16_t revid = HAL_GetREVID();
uint16_t devid = 0x0FFF & HAL_GetDEVID();
if (revid == 0x1001) mcurev = 'Z';
else /* 0x1000 */ mcurev = 'A';
printf("STM32U0xx DevID 0x%04x Rev.%c¥n",devid,mcurev);
printf("STM32U0xx UID 0x%08lx%08lx%08lx¥n",HAL_GetUIDw2(),HAL_GetUIDw1(),HAL_GetUIDw0());
printf("¥n");
#endif


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DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_OK;
uint32_t timer = SysTick->VAL + SD_DATATIMEOUT;

/* first ensure the SDCard is ready for a new operation */
while((SD_GetCardState() == SD_TRANSFER_BUSY))
{
if(timer < SysTick->VAL)
return RES_NOTRDY;
}

#if defined(SD_DMA_MODE) && !defined(SD_POLLING_MODE)

if((uintptr_t)buff & 0x3) /* Check 4Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count ; secNum++){

if(SD_ReadBlocks_DMA((uint32_t*)dmabuf, (uint32_t)(sector+secNum), 1)!= MSD_OK)
{
MSG_PRINTF("Read error on unaligned buffer¥n");
res = RES_ERROR;
}

memcpy(buff+secNum*SECTOR_SIZE, dmabuf, SECTOR_SIZE);
}
} else {
/* Aligned Buffer Address Case (Faster) */
if(SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Read error on DMA¥n");
res = RES_ERROR;
}
}
#else
if(SD_ReadBlocks((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Read error on polling¥n");
res = RES_ERROR;
}
#endif
return res;
}


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DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_ERROR;
uint32_t timer;


#if defined(SD_DMA_MODE) && !defined(SD_POLLING_MODE)
if((uintptr_t)buff & 0x3) /* Check 4Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count; secNum++){

memcpy(dmabuf, buff+(SECTOR_SIZE*secNum), SECTOR_SIZE);

if(SD_WriteBlocks_DMA((uint32_t*)dmabuf, (uint32_t)(sector+secNum), 1) != MSD_OK)
{
MSG_PRINTF("Write error on unaligned buffer¥n");
res = RES_ERROR;
}
}
} else {
if(SD_WriteBlocks_DMA((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Write error on DMA¥n");
res = RES_ERROR;
}
}
#else
if(SD_WriteBlocks((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Write error on polling¥n");
res = RES_ERROR;
}

#endif

/* ensure the SDCard is ready for a next operation */
timer = SysTick->VAL + SD_DATATIMEOUT;
res = RES_ERROR; /* Timeout */
/* block until SDIO IP is ready or a timeout occur */
while(timer > SysTick->VAL)
{
if(SD_GetCardState() == SD_TRANSFER_OK)
{
res = RES_OK;
break;
}
}

return res;
}

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./lib/ff/sdmmc_stm32h5.h


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	GPIO_InitTypeDef GPIO_InitStructure = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};

/* Enable CTRL line GPIO settings */
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_RES);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_CS);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_DC);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SCK);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDI);
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDO);

GPIO_InitStructure.Pin = CTRL_RES;
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStructure.Alternate = 0;
HAL_GPIO_Init(DISPLAY_PORT_RES, &GPIO_InitStructure);

GPIO_InitStructure.Pin = CTRL_CS;
HAL_GPIO_Init(DISPLAY_PORT_CS, &GPIO_InitStructure);
GPIO_InitStructure.Pin = CTRL_DC;
HAL_GPIO_Init(DISPLAY_PORT_DC, &GPIO_InitStructure);

/* Set peripheral clock */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
for(;;){
__NOP();
}
}
DISPLAY_PERIF_CLK(ENABLE);

/* Connect SPI pins to aletenate function */
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;

/* SPI SCK pin configuration */
GPIO_InitStructure.Pin = CTRL_SCK;
GPIO_InitStructure.Alternate = SRC_SCK;
HAL_GPIO_Init(DISPLAY_PORT_SCK, &GPIO_InitStructure);

/* SPI MOSI pin configuration */
GPIO_InitStructure.Pin = CTRL_SDI;
GPIO_InitStructure.Alternate = SRC_SDI;
HAL_GPIO_Init(DISPLAY_PORT_SDI, &GPIO_InitStructure);

/* SPI MISO pin configuration */
GPIO_InitStructure.Pin = CTRL_SDO;
GPIO_InitStructure.Alternate = SRC_SDO;
HAL_GPIO_Init(DISPLAY_PORT_SDO, &GPIO_InitStructure);

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	/* SPI configuration */
SpiHandle.Instance = LCD_SPI;
SpiHandle.Init.Mode = SPI_MODE_MASTER;
SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT;
SpiHandle.Init.CLKPolarity = SPI_POLARITY_HIGH;
SpiHandle.Init.CLKPhase = SPI_PHASE_2EDGE;
SpiHandle.Init.NSS = SPI_NSS_SOFT;
SpiHandle.Init.BaudRatePrescaler = SPI_BaudPrescale;
SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
SpiHandle.Init.TIMode = SPI_TIMODE_DISABLE;
SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
SpiHandle.Init.CRCPolynomial = 0x7;
SpiHandle.Init.CRCLength = SPI_CRC_LENGTH_8BIT;
SpiHandle.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
SpiHandle.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
SpiHandle.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
SpiHandle.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
SpiHandle.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
SpiHandle.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
SpiHandle.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; /* avoid glitch */
SpiHandle.Init.IOSwap = SPI_IO_SWAP_DISABLE;
SpiHandle.Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY;
SpiHandle.Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH;
if(HAL_SPI_Init(&SpiHandle) != HAL_OK)
{
/* Capture error */
while (1);
}

/* Enable SPI module */
LCD_SPI->CR1 |= SPI_CR1_SPE;
LCD_SPI->CR1 |= SPI_CR1_CSTART;

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SpiHandle.Init.BaudRatePrescaler 		= SPI_BaudPrescale;

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#define SPI_BaudPrescale	SPI_BAUDRATEPRESCALER_4 /* PLL1Q CLK 100MHz/4 = 25MHz */

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ST7789V2¤ÎSCL¤Î¥¯¥í¥Ã¥¯ºÇÂçÃͤÁ¤ã¤ó¤ÈÄ´¤Ù¤¿¤é¤Ê¤ó¤È60MHz¤Ç¤·¤¿¡ª¡ª¡ª
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	/* DMA controller clock enable */
__HAL_RCC_GPDMA1_CLK_ENABLE();

/* DMA interrupt init */
/* SPILCD_DMA_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SPILCD_DMA_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(SPILCD_DMA_IRQn);

/* Configure DMA request LcdDmaHandle */
LcdDmaHandle.Instance = SPILCD_DMA_CHANNEL;
LcdDmaHandle.Init.Request = SPILCD_DMA_REQEST;
LcdDmaHandle.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
LcdDmaHandle.Init.Direction = DMA_MEMORY_TO_PERIPH;
LcdDmaHandle.Init.SrcInc = DMA_SINC_INCREMENTED;
LcdDmaHandle.Init.DestInc = DMA_DINC_FIXED;
LcdDmaHandle.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
LcdDmaHandle.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
LcdDmaHandle.Init.Priority = DMA_LOW_PRIORITY_HIGH_WEIGHT;
LcdDmaHandle.Init.SrcBurstLength = 1;
LcdDmaHandle.Init.DestBurstLength = 1;
LcdDmaHandle.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
LcdDmaHandle.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
LcdDmaHandle.Init.Mode = DMA_NORMAL;
if (HAL_DMA_Init(&LcdDmaHandle) != HAL_OK)
{
for(;;){
__NOP();
}
}
__HAL_LINKDMA(&SpiHandle,hdmatx,LcdDmaHandle);

if (HAL_DMA_ConfigChannelAttributes(&LcdDmaHandle, DMA_CHANNEL_NPRIV) != HAL_OK)
{
for(;;){
__NOP();
}
}

/* SPI interrupt init */
/* SPILCD_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SPILCD_IRQn, 3, 1);
HAL_NVIC_EnableIRQ(SPILCD_IRQn);

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    LcdDmaHandle.Init.Direction 			= DMA_MEMORY_TO_PERIPH;
LcdDmaHandle.Init.SrcInc = DMA_SINC_INCREMENTED;
LcdDmaHandle.Init.DestInc = DMA_DINC_FIXED;
LcdDmaHandle.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
LcdDmaHandle.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;

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#define SPIx_TDR8			*(__IO uint8_t *) ((uint32_t)LCD_SPI+0x20)
#define SPIx_RDR8 *(__IO uint8_t *) ((uint32_t)LCD_SPI+0x30)


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inline void SendSPI(uint8_t dat)
{
/* Send byte through the SPI peripheral */
SPIx_TDR8 = dat;

/* Wait to receive a byte */
while (!(LCD_SPI->SR & (SPI_FLAG_RXP)));

/* Drain Rx FIFO */
SPIx_RDR8;
}

inline void SendSPI16(uint16_t dat)
{
SendSPI((uint8_t)(dat>>8));

SendSPI((uint8_t)dat);
}

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/**************************************************************************/
/*!
Write LCD Command.
*/
/**************************************************************************/
inline void ST7789V2_wr_cmd(uint8_t cmd)
{
ST7789V2_DC_CLR(); /* DC=L */
DISPLAY_ASSART_CS(); /* CS=L */

SendSPI(cmd);

DISPLAY_NEGATE_CS(); /* CS=H */
ST7789V2_DC_SET(); /* DC=H */
}

/**************************************************************************/
/*!
Write LCD Data and GRAM.
*/
/**************************************************************************/
inline void ST7789V2_wr_dat(uint8_t dat)
{
DISPLAY_ASSART_CS(); /* CS=L */

SendSPI(dat);

DISPLAY_NEGATE_CS(); /* CS=H */
}

/**************************************************************************/
/*!
Write LCD GRAM.
*/
/**************************************************************************/
inline void ST7789V2_wr_gram(uint16_t gram)
{
DISPLAY_ASSART_CS(); /* CS=L */

SendSPI16(gram);

DISPLAY_NEGATE_CS(); /* CS=H */
}



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/* DMA IRQ Handler */
void SPILCD_DMA_HANDLER(void)
{
HAL_DMA_IRQHandler(&LcdDmaHandle);
}
/* SPI IRQ Handler */
void SPILCD_IRQHandler(void)
{
HAL_SPI_IRQHandler(&SpiHandle);
}


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void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
if(hspi->Instance == LCD_SPI){
wTransferState = TRANSFER_COMPLETE;
}
}

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void lcd_dma_transfer(const uint8_t *buff,unsigned int count)
{
/* Disable SPI to change register */
LCD_SPI->CR1 &= ~(SPI_CR1_SPE);

/* Start DMA */
if (HAL_SPI_Transmit_DMA(&SpiHandle, buff, count) != HAL_OK)
{
for(;;){
__NOP();
}
}

/* Wait transfer complete */
while (wTransferState == TRANSFER_WAIT) {};

/* Restore transfer state */
wTransferState = TRANSFER_WAIT;

/* Restore nomal transfer settings */
LCD_SPI->CR2 = 0; /* Restore TSIZE */
LCD_SPI->CFG2 &= ~(SPI_CFG2_COMM_Msk); /* Restore FULL duplex mode */
LCD_SPI->CR1 |= SPI_CR1_SPE; /* Re-enable SPI module */
LCD_SPI->CR1 |= SPI_CR1_CSTART; /* Re-start SPI Trasfer ready */
}

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LCD_SPI->CR2 = 0; /* Restore TSIZE */
LCD_SPI->CFG2 &= ~(SPI_CFG2_COMM_Msk); /* Restore FULL duplex mode */
LCD_SPI->CR1 |= SPI_CR1_SPE; /* Re-enable SPI module */
LCD_SPI->CR1 |= SPI_CR1_CSTART; /* Re-start SPI Trasfer ready */

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/**************************************************************************/
/*!
@brief OCTO-SPI GPIO Configuration.
@param None.
@retval None.
*/
/**************************************************************************/
void OSPI_IoInit_If(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

/* Initializes the peripherals clock */
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI;
PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
for(;;);
}

/* Peripheral clock enable */
__HAL_RCC_OSPI1_CLK_ENABLE();

/* Alternate GPIO enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();

/* PD11 as OSPI_IO0 */
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPI1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);

/* PD12 as OSPI_IO1 */
GPIO_InitStruct.Pin = GPIO_PIN_12;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPI1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);

/* PE2 as OSPI_IO2(Need SB70 SolderBridge) */
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPI1;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);

/* PD13 as OSPI_IO3 */
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPI1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);

/* PB2 as OSPI_CLK */
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PG6 as OSPI_NCS */
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
}



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/**************************************************************************/
/*!
@brief Configure OCTO-SPI as Memory Mapped Mode.
Winbond W25Q128JVSIQ specific setting.
* Address size is 24bit(16MBytes).
* Initially sets QUAD-MODE(not need quadmode command).
* MAX 133MHz CLK.
* Support "XIP",thus suitable for MemoryMappedMode.
@param None.
@retval None.
*/
/**************************************************************************/
void Set_OSPI_MemoryMappedMode(void)
{
XSPI_RegularCmdTypeDef sCommand = {0};
XSPI_MemoryMappedTypeDef sMemMappedCfg = {0};
uint8_t reg_data =0;

/* Initialize OCTO-SPI I/O */
OSPI_IoInit_If();

/* Initialize OCTO-SPI */
hxspi.Instance = OCTOSPI1;
hxspi.Init.FifoThresholdByte = 1;
hxspi.Init.MemoryMode = HAL_XSPI_SINGLE_MEM;
hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MICRON;
hxspi.Init.MemorySize = 23; /* 128Mbit=16MByte=2^(23+1) W25Q128JVSIQ */
hxspi.Init.ChipSelectHighTimeCycle = 4; /* 4ClockCycle(16nSec@250MHzMAX) Need for W25Q128JVSIQ >10nSec@read */
hxspi.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE;
hxspi.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0;
hxspi.Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED;
hxspi.Init.ClockPrescaler = 1; /* 250MHzMAX/(1+1) = 125MHz (Allowed SDR Clock is 150MHz@3.3V) */
hxspi.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE;
hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_DISABLE;
hxspi.Init.ChipSelectBoundary = 0;
hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS;
hxspi.Init.Refresh = 0;
if (HAL_XSPI_Init(&hxspi) != HAL_OK)
{
for(;;);
}

/* Enable Reset --------------------------- */
/* Common Commands */
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
sCommand.IOSelect = HAL_XSPI_SELECT_IO_3_0;
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytes = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesWidth = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesDTRMode = HAL_XSPI_ALT_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x66; /* Reset Enable W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_XSPI_ADDRESS_NONE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_XSPI_DATA_NONE;
sCommand.DataLength = 0;
sCommand.DummyCycles = 0;

if (HAL_XSPI_Command(&hxspi, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Reset Device --------------------------- */
/* Common Commands */
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
sCommand.IOSelect = HAL_XSPI_SELECT_IO_3_0;
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytes = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesWidth = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesDTRMode = HAL_XSPI_ALT_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x99; /* Reset W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_XSPI_ADDRESS_NONE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_XSPI_DATA_NONE;
sCommand.DataLength = 0;
sCommand.DummyCycles = 0;

if (HAL_XSPI_Command(&hxspi, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Enter Quad-SPI Mode --------------------------- */
/* Common Commands */
sCommand.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
sCommand.IOSelect = HAL_XSPI_SELECT_IO_3_0;
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytes = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesWidth = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesDTRMode = HAL_XSPI_ALT_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x31; /* Set Status2 W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_XSPI_ADDRESS_NONE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_XSPI_INSTRUCTION_1_LINE;
sCommand.DataLength = 1;
sCommand.DummyCycles = 0;
reg_data = 0x02; /* Enable QuadI/O Mode */

if (HAL_XSPI_Command(&hxspi, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

if (HAL_XSPI_Transmit(&hxspi, ®_data, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Enter MemoryMappedMode --------------------------- */
/* Read Commands */
sCommand.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
sCommand.IOSelect = HAL_XSPI_SELECT_IO_3_0;
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_4_LINES;
sCommand.AlternateBytes = 0xFF; /* Need for Fast Read QUAD W25Q128JVSIQ */
sCommand.AlternateBytesWidth = HAL_XSPI_ALT_BYTES_8_BITS;
sCommand.AlternateBytesDTRMode = HAL_XSPI_ALT_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0xEB; /* Fast Read QUAD W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_XSPI_ADDRESS_4_LINES;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_XSPI_DATA_4_LINES;
sCommand.DataLength = 0;
sCommand.DummyCycles = 4; /* DUMMY 4Cycle for Fast Read QUAD W25Q128JVSIQ */

if(HAL_XSPI_Command(&hxspi, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Write Commands */
sCommand.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
sCommand.IOSelect = HAL_XSPI_SELECT_IO_3_0;
sCommand.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_XSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytes = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesWidth = HAL_XSPI_ALT_BYTES_NONE;
sCommand.AlternateBytesDTRMode = HAL_XSPI_ALT_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
sCommand.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
sCommand.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x32; /* Page Write QUAD W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_XSPI_DATA_4_LINES;
sCommand.DataLength = 0;
sCommand.DummyCycles = 0;

if(HAL_XSPI_Command(&hxspi, &sCommand, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Set OCTO-SPI as MemoryMappedMode */
sMemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE;
sMemMappedCfg.TimeoutPeriodClock = 0;
if(HAL_XSPI_MemoryMapped(&hxspi, &sMemMappedCfg) != HAL_OK)
{
for(;;);
}

}


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static void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct;
MPU_Attributes_InitTypeDef MPU_AttributesInit;

/* Configure region for UID,PACKAGE,FLASHSIZE and other registers */
/* Disable MPU */
HAL_MPU_Disable();

/* Define readonly access via MPU */
MPU_AttributesInit.Number = MPU_ATTRIBUTES_NUMBER0;
MPU_AttributesInit.Attributes = MPU_NOT_CACHEABLE;
HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit);

MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x08FFF800UL; /* UID ADDRESS and others */
MPU_InitStruct.LimitAddress = 0x08FFFFFFUL;
MPU_InitStruct.AccessPermission = MPU_REGION_ALL_RO;
MPU_InitStruct.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;

HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Enable MPU (any access not covered by any enabled region will cause a fault) */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}



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static int stm32h5x_read_idcode(struct flash_bank *bank, uint32_t *id)
{
struct target *target = bank->target;
struct cortex_m_common *cortex_m = target_to_cm(bank->target);
struct adiv5_ap *ap = cortex_m->armv7m.debug_ap;

/* DBGMCU_IDCODE cannot be read from AP1, read it from ROM Table */
target_addr_t dbgbase;
uint32_t apid;
int retval = dap_get_debugbase(ap, &dbgbase, &apid);
if (retval != ERROR_OK)
return retval;

target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;

/* PID Registers 0 to 3 are sufficient to identify the device */
uint32_t pid_regs[4];

retval = target_read_memory(target, base_addr + ARM_CS_PIDR0, 4, 4, (uint8_t *)pid_regs);
if (retval != ERROR_OK)
return retval;

uint64_t pid = (pid_regs[3] & 0xff) << 24
| (pid_regs[2] & 0xff) << 16
| (pid_regs[1] & 0xff) << 8
| (pid_regs[0] & 0xff);

uint16_t dev_id = pid & 0x0FFF;
uint8_t rev_id_major = pid >> 20 & 0xF;
uint8_t rev_id_minor = pid >> 28 & 0xF;
uint16_t rev_id = rev_id_major << 12 | rev_id_minor;

*id = rev_id << 16 | dev_id;

return retval;
}

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static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
{
int retval = ERROR_OK;
struct target *target = bank->target;

/* try reading possible IDCODE registers, in the following order */
uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_L5, DBGMCU_IDCODE_G0};

for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
retval = target_read_u32(target, dbgmcu_idcode[i], id);
if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
return ERROR_OK;
}

/* Workaround for STM32WL5x devices:
* DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
* to solve this read the UID64 (IEEE 64-bit unique device ID register) */

struct armv7m_common *armv7m = target_to_armv7m_safe(target);
if (!armv7m) {
LOG_ERROR("Flash requires Cortex-M target");
return ERROR_TARGET_INVALID;
}

/* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
* Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
if (cortex_m_get_partno_safe(target) == CORTEX_M0P_PARTNO &&
armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
uint32_t uid64_ids;

/* UID64 is contains
* - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
* - Bits 31:08 : STID (company ID) = 0x0080E1
* - Bits 07:00 : DEVID (device ID) = 0x15
*
* read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
*/
retval = target_read_u32(target, UID64_IDS, &uid64_ids);
if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
/* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
*id = DEVID_STM32WLE_WL5XX;
return ERROR_OK;
}
}

LOG_ERROR("can't get the device id");
return (retval == ERROR_OK) ? ERROR_FAIL : retval;
}

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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink-dap.cfg -c "transport select dapdirect_swd" -f target/stm32h5x_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.12.0+dev-00415-gacde409ba (2023-11-23-16:02)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
dapdirect_swd
Info : STLINK V3J13M4 (API v3) VID:PID 0483:3754
Info : Target voltage: 3.278828
Info : Unable to match requested speed 480 kHz, using 200 kHz
Info : Unable to match requested speed 480 kHz, using 200 kHz
Info : clock speed 200 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : [stm32h5x.cpu] Cortex-M33 r0p4 processor detected
Info : [stm32h5x.cpu] target has 8 breakpoints, 4 watchpoints
Info : starting gdb server for stm32h5x.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : Unable to match requested speed 480 kHz, using 200 kHz
Info : Unable to match requested speed 480 kHz, using 200 kHz
CPU in Non-Secure state
[stm32h5x.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xf9000000 pc: 0x08030dac msp: 0x20050000
Info : Unable to match requested speed 4000 kHz, using 3300 kHz
Info : Unable to match requested speed 4000 kHz, using 3300 kHz
Info : device idcode = 0x10000484 (STM32H56/H57xx - Rev A : 0x1000)
Info : TZEN = 0xC3 : TrustZone disabled by option bytes
Info : Product State = 0xED : 'Open'
Info : flash size = 2048kbytes
Info : flash mode : dual-bank
Info : Padding image section 1 at 0x0805aa8c with 4 bytes (bank write end alignment)
Warn : Adding extra erase range, 0x0805aa90 .. 0x0805bfff
Info : wrote 371344 bytes from file main.elf in 1.537886s (235.805 KiB/s)
Info : verified 371340 bytes in 0.903676s (401.291 KiB/s)
Info : Unable to match requested speed 480 kHz, using 200 kHz
Info : Unable to match requested speed 480 kHz, using 200 kHz
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:04

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/**************************************************************************/
/*!
@brief OCTO-SPI GPIO Configuration.
@param None.
@retval None.
*/
/**************************************************************************/
void OSPI_IoInit_If(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

/* Initializes the peripherals clock */
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI;
PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
for(;;);
}

/* Peripheral clock enable */
__HAL_RCC_OSPI1_CLK_ENABLE();

/* Alternate GPIO enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();

/* PE12 as OSPI_IO0 */
GPIO_InitStruct.Pin = GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);

/* PB0 as OSPI_IO1 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PE14 as OSPI_IO2 */
GPIO_InitStruct.Pin = GPIO_PIN_14;
GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);

/* PE15 as OSPI_IO3 */
GPIO_InitStruct.Pin = GPIO_PIN_15;
GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);

/* PB10 as OSPI_CLK */
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PA2 as OSPI_NCS */
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}

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/**************************************************************************/
/*!
@brief Configure OCTO-SPI as Memory Mapped Mode.
Winbond W25Q128JVSIQ specific setting.
* Address size is 24bit(16MBytes).
* Initially sets QUAD-MODE(not need quadmode command).
* MAX 133MHz CLK.
* Support "XIP",thus suitable for MemoryMappedMode.
@param None.
@retval None.
*/
/**************************************************************************/
void Set_OSPI_MemoryMappedMode(void)
{
OSPI_RegularCmdTypeDef sCommand = {0};
OSPI_MemoryMappedTypeDef sMemMappedCfg = {0};
uint8_t reg_data =0;

/* Initialize OCTO-SPI I/O */
OSPI_IoInit_If();

/* Initialize OCTO-SPI */
hospi.Instance = OCTOSPI1;
hospi.Init.FifoThreshold = 1;
hospi.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;
hospi.Init.DeviceSize = 24; /* 128Mbit=16MByte=2^24 W25Q128JVSIQ */
hospi.Init.ChipSelectHighTime = 2; /* 2ClockCycle(18nSec@110MHz) Need for W25Q128JVSIQ >10nSec@read */
hospi.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
hospi.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;
hospi.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
hospi.Init.ClockPrescaler = 2; /* 110MHzMAX/2 = 55MHz(MAX OSPI-CLK:90MHz) */
hospi.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE;
hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE;
hospi.Init.ChipSelectBoundary = 0;
hospi.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED;
hospi.Init.Refresh = 0;
if (HAL_OSPI_Init(&hospi) != HAL_OK)
{
for(;;);
}

/* Enable Reset --------------------------- */
/* Common Commands */
sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
sCommand.FlashId = HAL_OSPI_FLASH_ID_1;
sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_OSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytes = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesDtrMode = HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x66; /* Reset Enable W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_OSPI_ADDRESS_NONE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_OSPI_DATA_NONE;
sCommand.DummyCycles = 0;
sCommand.NbData = 0;

if (HAL_OSPI_Command(&hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Reset Device --------------------------- */
/* Common Commands */
sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
sCommand.FlashId = HAL_OSPI_FLASH_ID_1;
sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_OSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytes = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesDtrMode = HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x99; /* Reset W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_OSPI_ADDRESS_NONE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_OSPI_DATA_NONE;
sCommand.DummyCycles = 0;
sCommand.NbData = 0;

if (HAL_OSPI_Command(&hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Enter Quad-SPI Mode --------------------------- */
/* Common Commands */
sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
sCommand.FlashId = HAL_OSPI_FLASH_ID_1;
sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_OSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytes = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesDtrMode = HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x31; /* Set Status2 W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_OSPI_ADDRESS_NONE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.DummyCycles = 0;
sCommand.NbData = 1;
reg_data = 0x02; /* Enable QuadI/O Mode */

if (HAL_OSPI_Command(&hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

if (HAL_OSPI_Transmit(&hospi, &reg_data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Enter MemoryMappedMode --------------------------- */
/* Read Commands */
sCommand.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
sCommand.FlashId = HAL_OSPI_FLASH_ID_1;
sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_OSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_4_LINES;
sCommand.AlternateBytes = 0xFF; /* Need for Fast Read QUAD W25Q128JVSIQ */
sCommand.AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_8_BITS;
sCommand.AlternateBytesDtrMode = HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0xEB; /* Fast Read QUAD W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_OSPI_DATA_4_LINES;
sCommand.DummyCycles = 4; /* DUMMY 4Cycle for Fast Read QUAD W25Q128JVSIQ */
sCommand.NbData = 0;

if(HAL_OSPI_Command(&hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Write Commands */
sCommand.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
sCommand.FlashId = HAL_OSPI_FLASH_ID_1;
sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
sCommand.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_OSPI_DQS_DISABLE;
sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytes = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateBytesDtrMode = HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
/* Instruction */
sCommand.Instruction = 0x32; /* Page Write QUAD W25Q128JVSIQ */
/* Address */
sCommand.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
sCommand.Address = 0;
/* Data */
sCommand.DataMode = HAL_OSPI_DATA_4_LINES;
sCommand.DummyCycles = 0;
sCommand.NbData = 0;

if(HAL_OSPI_Command(&hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
for(;;);
}

/* Set OCTO-SPI as MemoryMappedMode */
sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
sMemMappedCfg.TimeOutPeriod = 0;
if(HAL_OSPI_MemoryMapped(&hospi, &sMemMappedCfg) != HAL_OK)
{
for(;;);
}

}

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	/* Making MicroSecond-Order Timer uses general purpose timer! */
/* Enable timer clock */
USEC_TIMx_CLKEN();

/* calculate TIMx(2 or 5) Prescaler clock(APB1) */
if(RCC->CFGR & RCC_CFGR_PPRE1){
if((RCC->CFGR & RCC_CFGR_PPRE1) == RCC_HCLK_DIV2){
cal_usec_divide = SystemCoreClock/2; /* (HCLK(=SYSCLK)*2 */
}
else if((RCC->CFGR & RCC_CFGR_PPRE1) == RCC_HCLK_DIV4){
cal_usec_divide = SystemCoreClock/4; /* (HCLK(=SYSCLK)*4)*2 */
}
else if((RCC->CFGR & RCC_CFGR_PPRE1) == RCC_HCLK_DIV8){
cal_usec_divide = SystemCoreClock/8; /* (HCLK(=SYSCLK)*8)*2 */
}
else if((RCC->CFGR & RCC_CFGR_PPRE1) == RCC_HCLK_DIV16){
cal_usec_divide = SystemCoreClock/16; /* (HCLK(=SYSCLK)*16)*2 */
}
}

/* usec wait timer settings */
TimHandle.Instance = USEC_TIMx;
TimHandle.Init.Period = UINT32_MAX;
TimHandle.Init.Prescaler = ((cal_usec_divide)/USEC_INTERVAL) - 1;
TimHandle.Init.ClockDivision = 0;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimHandle.Init.RepetitionCounter = 0;
TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&TimHandle) != HAL_OK)
{
/* Capture error */
while (1);
}

USEC_TIMx->CR1 &= ~(TIM_CR1_UIFREMAP); /* Disable UIF Remap(Must Need!) */
HAL_TIM_Base_Start(&TimHandle);

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#ifdef USE_DISPLAY_DMA_TRANSFER
/* DMA controller clock enable */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();

/* Configure DMA request LcdDmaHandle */
LcdDmaHandle.Instance = SPILCD_DMA_CHANNEL;
LcdDmaHandle.Init.Request = SPILCD_DMA_REQEST;
LcdDmaHandle.Init.Direction = DMA_MEMORY_TO_PERIPH;
LcdDmaHandle.Init.PeriphInc = DMA_PINC_DISABLE;
LcdDmaHandle.Init.MemInc = DMA_MINC_ENABLE;
LcdDmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
LcdDmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
LcdDmaHandle.Init.Mode = DMA_NORMAL;
LcdDmaHandle.Init.Priority = DMA_PRIORITY_MEDIUM;
if (HAL_DMA_Init(&LcdDmaHandle) != HAL_OK)
{
for(;;){
__NOP();
}
}
if (HAL_DMA_ConfigChannelAttributes(&LcdDmaHandle, DMA_CHANNEL_NPRIV) != HAL_OK)
{
for(;;){
__NOP();
}
}
__HAL_LINKDMA(&SpiHandle,hdmatx,LcdDmaHandle);

/* DMA interrupt init */
/* SPILCD_DMA_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SPILCD_DMA_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(SPILCD_DMA_IRQn);
#endif


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void Display_ChangeSDA_If(uint8_t sda_mode)
{
GPIO_InitTypeDef GPIO_InitStructure;

if(sda_mode == TFT_SDA_READ){
/* Enable CTRL Line GPIO Settings */
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDI);
GPIO_InitStructure.Pin = CTRL_SDI;
GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.Pull = GPIO_PULLUP;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStructure.Alternate = 0;
HAL_GPIO_Init(DISPLAY_PORT_SDI, &GPIO_InitStructure);
}

else {
/* Enable CTRL Line GPIO Settings */
#if defined(USE_SOFTWARE_SPI)
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDI);
GPIO_InitStructure.Pin = CTRL_SDI;
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStructure.Alternate = 0;
HAL_GPIO_Init(DISPLAY_PORT_SDI, &GPIO_InitStructure);

#else
/* Connect SPI pins to Alternate Function */
/* Restore SPI MOSI pin configuration */
DISPLAY_GPIOCLK_EN(DISPLAY_CLK_SDI);
DISPLAY_PERIF_CLK(ENABLE);
GPIO_InitStructure.Pin = CTRL_SDI;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStructure.Alternate = SRC_SDI;
HAL_GPIO_Init(DISPLAY_PORT_SDI, &GPIO_InitStructure);
#endif
}
}





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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink-dap.cfg -c "transport select dapdirect_swd" -f target/stm32c0x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.12.0+dev-00075-g79caea874 (2023-02-23-23:36)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
dapdirect_swd
Info : STLINK V2J38M27 (API v2) VID:PID 0483:374B
Info : Target voltage: 3.227154
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : clock speed 480 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x0bc11477
Info : [stm32c0x.cpu] Cortex-M0+ r0p1 processor detected
Info : [stm32c0x.cpu] target has 4 breakpoints, 2 watchpoints
Info : starting gdb server for stm32c0x.cpu on 3333
Info : Listening on port 3333 for gdb connections
[stm32c0x.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x08001918 msp: 0x20003000
Info : device idcode = 0x10006453 (STM32C03xx - Rev A : 0x1000)
Info : RDP level 0 (0xAA)
Info : flash size = 32 KiB
Info : flash mode : single-bank
Warn : Adding extra erase range, 0x08006070 .. 0x080067ff
Info : wrote 24688 bytes from file main.elf in 1.217141s (19.808 KiB/s)
Info : verified 24688 bytes in 0.269830s (89.350 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:02

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/**************************************************************************/
/*!
Read RAW MultiByteData Middlelevel.
*/
/**************************************************************************/
uint8_t I2CDev_ReadBytesRaw(uint8_t sla,uint8_t *data,uint8_t count)
{
/* Wait Bus Busy */
I2CDevTimer = I2CDEV_SHORT_TIMEOUT;
while((I2CDEV_PORT->ISR & I2C_ISR_BUSY))
{
if((I2CDevTimer--) == 0) return I2CDev_Timeout();
}

/* Send Slave Address and Memory Address */
/* Configure slave address, nbytes, NOLELOAD,NOAUTOSTOP */
I2C_TransferHandling(I2CDEV_PORT, sla|I2CDEV_SD_READ, count, 0, (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN));

for(int i = 0;i<(count-1);i++){
*data = I2CDev_RecvData(I2CDEV_ACK);
data++;
}
*data = I2CDev_RecvData(I2CDEV_NACK); /* Last data MUST be NACK */

/* Send Stop Condition */
I2CDev_StopCondition();

/* Wait until STOPF flag is reset */
I2CDevTimer = I2CDEV_SHORT_TIMEOUT;
while(!(I2CDEV_PORT->ISR & I2C_FLAG_STOPF))
{
if(I2CDev_ReadNAck() ==I2CDEV_NACK) return I2CDev_Timeout();
if((I2CDevTimer--) == 0) return I2CDev_Timeout();
}

/* Clear STOP Flag */
I2CDEV_PORT->ICR =I2C_ISR_STOPF;

/* Clear Configuration Register 2 */
I2CDEV_PORT->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));

return 1;
}


¢¨Á÷¿®¢¨

/**************************************************************************/
/*!
Write RAW MultiBytes Middlelevel.
*/
/**************************************************************************/
uint8_t I2CDev_WriteBytesRaw(uint8_t sla,uint8_t *data,uint8_t count)
{
/* Wait Bus Busy */
I2CDevTimer = I2CDEV_SHORT_TIMEOUT;
while((I2CDEV_PORT->ISR & I2C_ISR_BUSY))
{
if((I2CDevTimer--) == 0) return I2CDev_Timeout();
}

/* Send Slave Address and Memory Address */
/* Configure slave address, nbytes, RELOAD,AUTOSTOP,AUTOSTART */
I2C_TransferHandling(I2CDEV_PORT, sla|I2CDEV_SD_WRITE, count, I2C_CR2_AUTOEND|I2C_CR2_RELOAD, I2C_CR2_START);

/* Send multibytes datas */
for(int i = 0; i < count ; i++){
/* Wait until TXIS flag is set */
I2CDevTimer = I2CDEV_SHORT_TIMEOUT;
while(!(I2CDEV_PORT->ISR & I2C_ISR_TXIS))
{
if(I2CDev_ReadNAck() == I2CDEV_NACK){
/* Clear STOP Flag */
I2CDEV_PORT->ICR =I2C_ISR_NACKF;
/* Clear STOP Flag */
I2CDEV_PORT->ICR =I2C_ISR_STOPF;
/* Clear TXE Flag */
I2CDEV_PORT->ISR |=I2C_ISR_TXE;

/* Clear Configuration Register 2 */
I2CDEV_PORT->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));

return 0;
}

if((I2CDevTimer--) == 0) return I2CDev_Timeout();
}
I2CDev_SendData(*data);
data++;
//I2C_WaitFlag(I2C_ISR_TCR); /* Notneeded in auto STOP */
}

/* Send Stop Condition */
//I2CDev_StopCondition(); /* Notneeded in auto STOP */

/* Wait until STOPF flag is reset */
I2CDevTimer = I2CDEV_SHORT_TIMEOUT;
while(!(I2CDEV_PORT->ISR & I2C_FLAG_STOPF))
{
if(I2CDev_ReadNAck() ==I2CDEV_NACK) return I2CDev_Timeout();
if((I2CDevTimer--) == 0) return I2CDev_Timeout();
}

/* Clear STOP Flag */
I2CDEV_PORT->ICR |=I2C_ISR_STOPF;

/* Clear Configuration Register 2 */
I2CDEV_PORT->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));

return 1;
}

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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/vsllink_swd.cfg -f target/stm32g0x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.11.0-rc1+dev-00032-gbd1adcffe (2021-01-23-19:37)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : VSLLink SWD mode enabled
swd
Info : Versaloon(0x15)by Simon(compiled on Sep 16 2014)
Info : USB_TO_XXX abilities: 0x0000176E:0x010001EF:0xC0000007
Info : clock speed 500 kHz
Info : SWD DPIDR 0x0bc11477
Info : stm32g0x.cpu: hardware has 4 breakpoints, 2 watchpoints
Info : starting gdb server for stm32g0x.cpu on 3333
Info : Listening on port 3333 for gdb connections
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x08000c9c msp: 0x20002000
Info : device idcode = 0x10016466 (STM32G03/G04xx - Rev Z : 0x1001)
Info : flash size = 32kbytes
Info : flash mode : single-bank
Info : Padding image section 1 at 0x08000eac with 4 bytes (bank write end alignment)
Warn : Adding extra erase range, 0x08000eb0 .. 0x08000fff
Info : wrote 3760 bytes from file main.elf in 0.188402s (19.490 KiB/s)
Info : verified 3756 bytes in 0.029309s (125.148 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:01



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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/stlink.cfg -c "transport select hla_swd" -f target/stm32g0x_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.11.0-rc1+dev-00032-gbd1adcffe (2021-01-23-19:37)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
hla_swd
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : clock speed 500 kHz
Info : STLINK V2J33M25 (API v2) VID:PID 0483:3752
Info : Target voltage: 3.272439
Info : stm32g0x.cpu: hardware has 4 breakpoints, 2 watchpoints
Info : starting gdb server for stm32g0x.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x08000c9c msp: 0x20002000
Info : device idcode = 0x10016466 (STM32G03/G04xx - Rev Z : 0x1001)
Info : flash size = 32kbytes
Info : flash mode : single-bank
Info : Padding image section 1 at 0x08000eac with 4 bytes (bank write end alignment)
Warn : Adding extra erase range, 0x08000eb0 .. 0x08000fff
Info : wrote 3760 bytes from file main.elf in 0.156605s (23.447 KiB/s)
Info : verified 3756 bytes in 0.031977s (114.706 KiB/s)
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:01


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¤Ê¤¼¤«¤½¤¦¤ÏÌä²°¤¬²·¤µ¤º¡¢»ä¤¬»î¤·¤¿¸Â¤ê¤Ç¤Ïɬ¤ºClean¤â¤·¤Ê¤±¤é¤Ð¤Ê¤é¤Ê¤¤¤³¤È¤¬
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DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_OK;
uint32_t timer = SysTick->VAL + SD_DATATIMEOUT;

/* first ensure the SDCard is ready for a new operation */
while((SD_GetCardState() == SD_TRANSFER_BUSY))
{
if(timer < SysTick->VAL)
return RES_NOTRDY;
}

#if defined(SD_DMA_MODE) && !defined(SD_POLLING_MODE)
/*
Force Cache Data Lines content write back to memory and Invalidate them.
Someone (CPU) might be still accessing those cache lines so we need to
flush/clean recent content to memory and purge/invalid cache lines before
allowing Hardware to access RAM.
*/
if((uintptr_t)buff & 0x3) /* Check 4Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count ; secNum++){

SCB_InvalidateDCache_by_Addr ((uint32_t*)dmabuf, SECTOR_SIZE);

if(SD_ReadBlocks_DMA((uint32_t*)dmabuf, (uint32_t)(sector+secNum), 1)!= MSD_OK)
{
MSG_PRINTF("Read error on unaligned buffer¥n");
res = RES_ERROR;
}

memcpy(buff+secNum*SECTOR_SIZE, dmabuf, SECTOR_SIZE);
}
} else {
/* Aligned Buffer Address Case (Faster) */
SCB_CleanInvalidateDCache_by_Addr((uint32_t*)buff, count * SECTOR_SIZE);

if(SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Read error on DMA¥n");
res = RES_ERROR;
}
}
#else
if(SD_ReadBlocks((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Read error on polling¥n");
res = RES_ERROR;
}
#endif
return res;
}

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READ¥¢¥¯¥·¥ç¥ó¤ò¤È¤ëÁ°¤ËSCB_CleanInvalidateDCache_by_Addr()¤ò¼Â¹Ô¤·¤Þ¤¹¡£
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³Ð¤¨¤Æ¤ª¤­¤Þ¤·¤·¤ç¤¦!¤½¤¦¤»¤¶¤ë¤òÆÀ¤Ê¤«¤Ã¤¿Î㤬¤³¤Á¤é¤ÎµÄÏÀ¤Ë¤â¤¢¤ê¤Þ¤¹¤¬ÀµÄ¾
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¤½¤ó¤Ç¤â¤Ã¤ÆCleanInvalidate¤·¤¿¤³¤È¤Ë¤è¤ë¥­¥ã¥Ã¥·¥å¥³¥ó¥È¥í¡¼¥ë¤Ë¤è¤ë
¥ª¡¼¥Ð¡¼¥Ø¥Ã¥É¤¬·üÇ°¤µ¤ì¤Þ¤¹¤¬H7¤ÏCPU¤Î¥³¥¢¤Î®ÅÙ¤¬MAX480MHz¤â½Ð¤ë¤Î¤Ç
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¡üDMA¤ÇÁ÷¿®¤¹¤ë¾ì¹ç(SDMMC¤ÎIDMA¤Î¾ì¹ç)
DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_ERROR;
uint32_t timer;


#if defined(SD_DMA_MODE) && !defined(SD_POLLING_MODE)
/*
Force Cache Data Lines content write back to memory.
Someone (CPU) might be still accessing those cache lines so we need to
flush/clean recent content to memory before
allowing Hardware to access RAM.
*/
if((uintptr_t)buff & 0x3) /* Check 4Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count; secNum++){

memcpy(dmabuf, buff+(SECTOR_SIZE*secNum), SECTOR_SIZE);

SCB_CleanDCache_by_Addr((uint32_t*)dmabuf, SECTOR_SIZE);

if(SD_WriteBlocks_DMA((uint32_t*)dmabuf, (uint32_t)(sector+secNum), 1) != MSD_OK)
{
MSG_PRINTF("Write error on unaligned buffer¥n");
res = RES_ERROR;
}
}
} else {

SCB_CleanDCache_by_Addr((uint32_t*)buff, count * SECTOR_SIZE);

if(SD_WriteBlocks_DMA((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Write error on DMA¥n");
res = RES_ERROR;
}
}
#else
if(SD_WriteBlocks((uint32_t*)buff, (uint32_t)sector, count) != MSD_OK)
{
MSG_PRINTF("Write error on polling¥n");
res = RES_ERROR;
}

#endif

/* ensure the SDCard is ready for a next operation */
timer = SysTick->VAL + SD_DATATIMEOUT;
res = RES_ERROR; /* Timeout */
/* block until SDIO IP is ready or a timeout occur */
while(timer > SysTick->VAL)
{
if(SD_GetCardState() == SD_TRANSFER_OK)
{
res = RES_OK;
break;
}
}

return res;
}

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WRITE¤Î¤Û¤¦¤Ïñ½ãÌÀ²÷¡¢Å¾Á÷Á°¤ËClean¤·¤Æ¤ä¤ë¤À¤±¤Ç¤¹¡ª
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¡üDMA¤ÇÁ÷¿®¤¹¤ë¾ì¹ç(SAI¤ÎCircularDMA¤Î¾ì¹ç)
¥é¥¤¥È¥¹¥ë¡½¤¬»È¤¨¤Ê¤¯¤Ê¤Ã¤¿¤»¤¤¤Ç¤¤¤í¤ó¤Ê¥³¡¼¥É¤Ë¥­¥ã¥Ã¥·¥å¥³¥ó¥È¥í¡¼¥ë¤ò
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²»¸»¤ÎBeachBoys¤Î¥Ï¡¼¥â¥Ë¥Ã¥¯¡¦¥µ¥¦¥ó¥É¤¬ŽÌŽÞŽËŽÞŽËŽÞŽËŽÞŽ¯ŽÌŽÞŽ¯¤È¤¤¤¦¤²¤ê¤¦¤ó¤Á¤ß¤¿¤¤¤Ê
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ÌäÂê¤ÏÁÞÆþ¤¹¤ë²Õ½ê¤Ç¤¹¡£

/* on the first buffer fill up,start the dma transfer */
if(EVAL_AUDIO_Init(OUTPUT_DEVICE_BOTH, DEFAULT_VOLUME, (uint32_t)mp3FrameInfo.samprate))
{
MSG_PRINTF("Mp3Decode: audio init failed¥r¥n");
nResult = -4;
break;
}
/* I2S DMA Transfer First Trigger */
#if defined(STM32H7XX)
SCB_CleanDCache_by_Addr((uint32_t*)g_pMp3DmaBuffer, MP3_DMA_BUFFER_SIZE);
#endif
/* Needed to AAC_DMA_BUFFER_SIZE*2,16-bits audio data size(2Byte) */
/* See more detail,BSP_AUDIO_OUT_Play() */
EVAL_AUDIO_Play(g_pMp3DmaBuffer, MP3_DMA_BUFFER_SIZE*2);

¢¬Å¾Á÷¤Ê¤Î¤ÇClean¤Î¤ß¤Ç¤ª£ë(mp3.support.c¤Ë¤Æ)
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if(unDmaBufMode == INIT_RINGBUF || unDmaBufMode == FULL_RINGBUF)
{
/* Check FirstHalf Transfer in LastHalf and BufferInit Mode */
if(em & TRANSFER_FIRST_HALF)
{
MSG_PRINTF("Mp3Decode: DMA out of sync (expected TC, got HT)¥r¥n");
nResult = -3;
break;
}
else{
g_pMp3DmaBufferPtr = g_pMp3DmaBuffer + (MP3_DMA_BUFFER_SIZE/2); /* 16bit address pointer calc */
#if defined(STM32H7XX)
SCB_CleanDCache_by_Addr((uint32_t*)g_pMp3DmaBufferPtr, MP3_DMA_BUFFER_SIZE);
#endif
}
}
else /* unDmaBufMode == HALF_RINGBUF */
{
/* Check LastHalf Transfer in FirstHalf Mode */
if(em & TRANSFER_LAST_HALF)
{
MSG_PRINTF("Mp3Decode: DMA out of sync (expected HT, got TC)¥r¥n");
nResult = -3;
break;
}
else{
g_pMp3DmaBufferPtr = g_pMp3DmaBuffer;
#if defined(STM32H7XX)
SCB_CleanDCache_by_Addr((uint32_t*)g_pMp3DmaBufferPtr, MP3_DMA_BUFFER_SIZE);
#endif
}

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g_pMp3DmaBufferPtr¤Ë¼¡¤ËžÁ÷¤¹¤ë¥Ð¥Ã¥Õ¥¡¤Î¥¢¥É¥ì¥¹¤ò¥³¥Ô¡¼¤·¤¿¸åClean¤Ç¤¹¡£
g_pMp3DmaBufferPtr¤Ïuint16_t¤Î¥Ý¥¤¥ó¥¿¤Ê¤Î¤ÇÃí°Õ¤¬É¬ÍפǤ¹¡£


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¥é¥¤¥È¥¹¥ë¡¼¤¬»È¤¨¤Ê¤¯¤Ê¤Ã¤¿ÊÀ³²¤ÏDMA¤ÈƱ¤¸¤¯¥­¥ã¥Ã¥·¥å¥³¥Ò¡¼¥ì¥ó¥·¡¼¤ò
µá¤á¤é¤ì¤ëLTDC¤Ë¤âÇȵڤ·¤Þ¤¹¡£

static void disp_blt (
int left, /* Left end (-32768 to 32767) */
int right, /* Right end (-32768 to 32767, >=left) */
int top, /* Top end (-32768 to 32767) */
int bottom, /* Bottom end (-32768 to 32767, >=right) */
const uint16_t *pat /* Pattern data */
)
{
int yc, xc, xs;
#if !defined(USE_TFT_FRAMEBUFFER)
int xl;
uint16_t pd;
#endif

if (left > right || top > bottom) return; /* Check varidity */
if (left > MaskR || right < MaskL || top > MaskB || bottom < MaskT) return; /* Check if in active area */

yc = bottom - top + 1; /* Vertical size */
xc = right - left + 1; xs = 0; /* Horizontal size and skip */

if (top < MaskT) { /* Clip top of source image if it is out of active area */
pat += xc * (MaskT - top);
yc -= MaskT - top;
top = MaskT;
}
if (bottom > MaskB) { /* Clip bottom of source image if it is out of active area */
yc -= bottom - MaskB;
bottom = MaskB;
}
if (left < MaskL) { /* Clip left of source image if it is out of active area */
pat += MaskL - left;
xc -= MaskL - left;
xs += MaskL - left;
left = MaskL;
}
if (right > MaskR) { /* Clip right of source image it is out of active area */
xc -= right - MaskR;
xs += right - MaskR;
right = MaskR;
}
Display_rect_if(left, right, top, bottom); /* Set rectangular area to fill */
#if defined(STM32F7XX) || defined(STM32H7XX) /* Flush Cache Datas */
SCB_CleanDCache_by_Addr((uint32_t*)pat, xc*yc*2);
#endif
#if defined(USE_TFT_FRAMEBUFFER)
Display_wr_block_if((uint8_t*)pat, xc*yc);
#else
do { /* Send image data */
xl = xc;
do {
pd = *pat++;
Display_wr_dat_if(pd);
} while (--xl);
pat += xs;
} while (--yc);
#endif
}

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	/* Configure the MPU attributes as Write-Back/No-Write-Allocate for AXI-SRAM D1 */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x24000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
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MPU_InitStruct.IsBufferable 	= MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;

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	/* Configure the MPU attributes as Write-Back/No-Write-Allocate for AHB-SRAM1 D2 */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x30000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Configure the MPU attributes as Write-Back/No-Write-Allocate for AHB-SRAM2 D2 */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x30020000;
MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Configure the MPU attributes as Write-Back/No-Write-Allocate for AHB-SRAM3 D2 */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x30040000;
MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Configure the MPU attributes as Write-Back/No-Write-Allocate for AHB-SRAM4 D3 */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x38000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER4;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

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	/* External-Memories cache setting */
/* Configure the MPU attributes as Write-Back/No-Write-Allocate for External SDRAM */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0xD0000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_32MB; /* STM32H747I-Disco have 32Mbyte SDRAM */
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER6;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; /* MUST be No-WriteAllocation to avoid collision LTDC-Hostage */
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* External-Memories cache setting */
/* Configure the MPU attributes as Write-Back for QSPI-DirectRemapping(ReadOnly) */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x90000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_128MB; /* STM32H747I-Disco have 64*2=128MByte QSPI-ROM */
MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RO_URO;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER7;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

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/* Linker script Upperside for STM32H747XIH6		*/
/* Nemui Trinomius (http://nemuisan.blog.bai.ne.jp) */

OUTPUT_FORMAT ("elf32-littlearm")

/* Memory Spaces Definitions */
MEMORY
{
/* Instruction TCM SRAM */
ITCM_RAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64k
/* Data TCM SRAM */
DTCM_RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128k
/* AXI-SRAM D1 Domain */
AXI_SRAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512k
/* AHB-SRAM1 D2 Domain */
SRAM1_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 128k
/* AHB-SRAM2 D2 Domain */
SRAM2_D2 (xrw) : ORIGIN = 0x30020000, LENGTH = 128K
/* SRAM3 D2 Domain */
SRAM3_D2 (xrw) : ORIGIN = 0x30040000, LENGTH = 32k
/* SRAM4 D3 Domain */
SRAM4_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64k
/* Backup SRAM */
BKP_SRAM (rw) : ORIGIN = 0x38800000, LENGTH = 4k
/* External SDRAM(FMC) */
EXT_SDRAM (xrw) : ORIGIN = 0xD0000000, LENGTH = 32M
/* Main Embedded Dual-Bank FlashROM */
FLASH_ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2M
/* External Dual-Mode QSPI-ROM */
QSPI_ROM (rx) : ORIGIN = 0x90000000, LENGTH = 128M
}

/* higher address of the stack bottom,AAPCS said "stack MUST BE 8byte alignment". */
_estack = (ORIGIN(DTCM_RAM)+LENGTH(DTCM_RAM)) & ~ 0x7;

/* higher address of the heap end */
_eheap = ORIGIN(AXI_SRAM)+LENGTH(AXI_SRAM);


/* include the section management sub-script */
INCLUDE "STM32H7xxxx_FLASH.ld"


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/* Defines -------------------------------------------------------------------*/
/**
* @brief System Clock Configuration
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 400000000 (Cortex-M7 CPU Clock,upto 480MHz)
* HCLK(Hz) = 200000000 (Cortex-M4 CPU, Bus matrix Clocks,upto 200MHz)
* AHB Prescaler = 2 (AHB/AXI Bus Matrix Clock upto 200MHz)
* D1 APB3 Prescaler = 2 (APB3 Clock upto 100MHz)
* D2 APB1 Prescaler = 2 (APB1 Clock upto 100MHz)
* D2 APB2 Prescaler = 2 (APB2 Clock upto 100MHz)
* D3 APB4 Prescaler = 2 (APB4 Clock upto 100MHz)
* HSE Frequency(Hz) = 25000000
* VCO Frequency = 800000000 (160*5)
* PLL_M = 5
* PLL_N = 160
* PLL_P = 2
* PLL_Q = 4
* PLL_R = 2
* VDD(V) = 3.3
* Flash Latency(WS) = 4
* @param None
* @retval None
*/
#define PLL1_M 5
#define PLL1_N 160
#define PLL1_P 2
#define PLL1_Q 4
#define PLL1_R 2
#define PLL1_FRACN 0
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static void LED_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStructure;

/* Enable GPIO_LED clock */
GPIO_LED_CLKEN();

/* Configure GPIO for LEDs as Output push-pull */
GPIO_InitStructure.Pin = LED_D1;
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStructure.Alternate = 0;
HAL_GPIO_Init(GPIO_LED1, &GPIO_InitStructure);
LED_D1_OFF();

GPIO_InitStructure.Pin = LED_D2;
HAL_GPIO_Init(GPIO_LED2, &GPIO_InitStructure);
LED_D2_OFF();
GPIO_InitStructure.Pin = LED_D3;
HAL_GPIO_Init(GPIO_LED3, &GPIO_InitStructure);
LED_D3_OFF();
GPIO_InitStructure.Pin = LED_D4;
HAL_GPIO_Init(GPIO_LED4, &GPIO_InitStructure);
LED_D4_OFF();
}

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static void KEY_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStructure;

/* Enable GPIO_LED clock */
RCC->AHB4ENR |= (RCC_AHBPeriph_GPIO_KEY_USER1);
RCC->AHB4ENR |= (RCC_AHBPeriph_GPIO_KEY_SEL);
RCC->AHB4ENR |= (RCC_AHBPeriph_GPIO_KEY_DOWN);
RCC->AHB4ENR |= (RCC_AHBPeriph_GPIO_KEY_LEFT);
RCC->AHB4ENR |= (RCC_AHBPeriph_GPIO_KEY_RIGHT);
RCC->AHB4ENR |= (RCC_AHBPeriph_GPIO_KEY_UP);

/* Configure GPIO for Key Input */
GPIO_InitStructure.Pin = KEY_USER1;
GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;;
GPIO_InitStructure.Alternate = 0;
HAL_GPIO_Init(GPIO_KEY_USER1, &GPIO_InitStructure);

GPIO_InitStructure.Pull = GPIO_PULLUP;
GPIO_InitStructure.Pin = KEY_SEL_PIN;
HAL_GPIO_Init(GPIO_KEY_SEL, &GPIO_InitStructure);
GPIO_InitStructure.Pin = KEY_DOWN_PIN;
HAL_GPIO_Init(GPIO_KEY_DOWN, &GPIO_InitStructure);
GPIO_InitStructure.Pin = KEY_LEFT_PIN;
HAL_GPIO_Init(GPIO_KEY_LEFT, &GPIO_InitStructure);
GPIO_InitStructure.Pin = KEY_RIGHT_PIN;
HAL_GPIO_Init(GPIO_KEY_RIGHT, &GPIO_InitStructure);
GPIO_InitStructure.Pin = KEY_UP_PIN;
HAL_GPIO_Init(GPIO_KEY_UP, &GPIO_InitStructure);
}

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/* Macros */
/* uncomment to enable joy input */
//#define USE_HWKEY_INPUT_SUPPORT

/* ITCM Fastest call for IRQ */
#define ITCM __attribute__ ((section (".itcm")))
//#define ITCM __attribute__ ((long_call, section (".itcm")))

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	/* Making MilliSecond-Order Timer */
/* Select Clock Source */
SystemCoreClockUpdate();
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* Setup SysTick Timer for 1 msec interrupts */
if (SysTick_Config(SystemCoreClock/interval))
{
/* Capture error */
while (1);
}

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	/* Making MicroSecond-Order Timer uses general purpose timer! */
/* Enable timer clock */
USEC_TIMx_CLKEN();

/* calculate TIMx(2~5) Prescaler clock(D2 Domain) */
if(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1){
if((RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) == RCC_D2CFGR_D2PPRE1_DIV2){
cal_usec_divide = SystemCoreClock/2; /* (HCLK(=SYSCLK/2)*2)*2 */
}
else if((RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) == RCC_D2CFGR_D2PPRE1_DIV4){
cal_usec_divide = SystemCoreClock/4; /* (HCLK(=SYSCLK/2)*4)*2 */
}
else if((RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) == RCC_D2CFGR_D2PPRE1_DIV8){
cal_usec_divide = SystemCoreClock/8; /* (HCLK(=SYSCLK/2)*8)*2 */
}
else if((RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) == RCC_D2CFGR_D2PPRE1_DIV16){
cal_usec_divide = SystemCoreClock/16; /* (HCLK(=SYSCLK/2)*16)*2 */
}
}

TimHandle.Instance = USEC_TIMx;
TimHandle.Init.Period = UINT32_MAX;
TimHandle.Init.Prescaler = ((cal_usec_divide)/USEC_INTERVAL) - 1;
TimHandle.Init.ClockDivision = 0;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimHandle.Init.RepetitionCounter = 0;
if (HAL_TIM_Base_Init(&TimHandle) != HAL_OK)
{
/* Capture error */
while (1);
}

USEC_TIMx->CR1 &= ~(TIM_CR1_UIFREMAP); /* Disable UIF Remap(Must Need!) */

HAL_TIM_Base_Start(&TimHandle);

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#if defined(USE_STM32H747I_DISCO)
#define UART_DEFAULT_NUM 1
#define UARTx USART1
#define USARTx_IRQHandler USART1_IRQHandler
#define USARTx_CLKEN() ¥
/* Enable GPIO clock(UART_TX) */ ¥
RCC->AHB4ENR |= (RCC_AHB4ENR_GPIOAEN); ¥
/* Enable GPIO clock(UART_RX) */ ¥
RCC->AHB4ENR |= (RCC_AHB4ENR_GPIOAEN); ¥
/* Enable UART clock */ ¥
RCC->APB2ENR |= (RCC_APB2ENR_USART1EN);
#define USART_TxPin GPIO_PIN_9
#define USART_RxPin GPIO_PIN_10
#define USART_TxPort GPIOA
#define USART_RxPort GPIOA
#define USART_TXALT GPIO_AF7_USART1
#define USART_RXALT GPIO_AF7_USART1

/* This is the ARDUINO Option(not used) */
//#define UART_DEFAULT_NUM 8
//#define UARTx USART8
//#define USARTx_IRQHandler USART8_IRQHandler

#else
#error "Select or make board settings!!"
#endif

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#if defined(UART_INTERRUPT_MODE)
/**************************************************************************/
/*!
@brief Handles UARTx global interrupt request.
@param None.
@retval None.
*/
/**************************************************************************/
ITCM void USARTx_IRQHandler(void)
{
uint32_t IntStat = UARTx->ISR;

if(IntStat & USART_ISR_RXNE_RXFNE)
{
/* Clear Errors */
UARTx->ICR = USART_ICR_ORECF | USART_ICR_NECF | USART_ICR_FECF | USART_ICR_PECF;

/* Advance buffer head. */
unsigned int tempRX_Head = ((&USARTx_Buf)->RX_Head + 1) & (UART_BUFSIZE-1);

/* Check for overflow. */
unsigned int tempRX_Tail = (&USARTx_Buf)->RX_Tail;
uint8_t data = UARTx->RDR;

if (tempRX_Head == tempRX_Tail) {
/* Overflow MAX size Situation */
/* Disable the UART Receive interrupt */
UARTx->CR1 &= ~(USART_CR1_RXNEIE);
}else{
(&USARTx_Buf)->RX[(&USARTx_Buf)->RX_Head] = data;
(&USARTx_Buf)->RX_Head = tempRX_Head;
}
}

if(IntStat & USART_ISR_TXE_TXFNF)
{
/* Check if all data is transmitted. */
unsigned int tempTX_Tail = (&USARTx_Buf)->TX_Tail;
if ((&USARTx_Buf)->TX_Head == tempTX_Tail){
/* Overflow MAX size Situation */
/* Disable the UART Transmit interrupt */
UARTx->CR1 &= ~(USART_CR1_TXEIE);
}else{
/* Start transmitting. */
uint8_t data = (&USARTx_Buf)->TX[(&USARTx_Buf)->TX_Tail];
UARTx->TDR = data;

/* Advance buffer tail. */
(&USARTx_Buf)->TX_Tail = ((&USARTx_Buf)->TX_Tail + 1) & (UART_BUFSIZE-1);
}
}
}
#endif

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/**************************************************************************/
/*!
@brief Copy Time-Critical codes into ITCM-RAM.
@param None.
@retval None.
*/
/**************************************************************************/
static void datacopy(unsigned int romstart, unsigned int start, unsigned int len)
{
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
/* _stitcm,_sitcm,_eitcm are MUST be decrare in likerscript file */
static void ITCM_Datainit(void)
{
unsigned int *LoadAddr, *ExeAddr, *EndAddr, SectionLen;

/* Copy ITCM Codes into ITCM-RAM */
LoadAddr = &_stitcm;
ExeAddr = &_sitcm;
EndAddr = &_eitcm;
SectionLen = (void*)EndAddr - (void*)ExeAddr;
datacopy((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
}

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FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Dec 6 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 14338 kB/sec.
>ds 0
rc=0
Drive size: 1947648 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Byte)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 00 5E 00 32 5B 59 A3 B6 FF FF FF 80 0A 40 00 6D .^.2[Y.......@.m
CID:
00000000 58 44 44 44 44 49 4E 43 30 6D 6D D4 59 01 0C 49 XDDDDINC0mm.Y..I

Parsing SD CID Register
Manufacturer ID :0x58
OEM/Application ID :DD
Product Name :DDINC
Product HwRev :3
Product SwRev :0
Serial Number :0x6D6DD459
DateCode.Month :12
DateCode.Year :2016

OCR:
00000000 80 FF 80 00 ....
SD Status:
00000000 80 00 00 00 00 00 00 28 03 03 90 02 00 AB 00 00 .......(........
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 25 80 00 01 00 00 00 .%......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Spec Version X :0
SD Security :2
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDSC Card!
Available NS(or HS) Mode Only.
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(¤â¤Á¤í¤ómakefile¤ÎÀßÄê¤ÇF746-G²½¤â²Äǽ¤Ç¤¹)¤Î¤Ç¼êÁ°Ì£Á¹¤Ç¤¢¤ê¤Þ¤¹¤¬
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STM32F4¥·¥ê¡¼¥º¤ò»È¤Ã¤Æ¤ß¤ë15 - FatFs¤ÈSD¥«¡¼¥ÉºÆ¹Í¤½¤Î4(SD¥«¡¼¥É¤ò¼êÅö¤¿¤ê¤·¤À¤¤Æɤ߽Ф·¤Æ¤ß¤ë) -

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STM32F4¤ò»È¤Ã¤ÆSD¥«¡¼¥É¤Î¥«¡¼¥É¾ðÊó¤òÆɤ߽Ф·¤¿¤êÆɤ߼è¤ê®ÅÙ¤ÎÈæ³Ó¤ò
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MMC¤«¤é»Ï¤Þ¤ê10ǯ°Ê¾åÁ°¤ÎSD¥«¡¼¥É¤äºÇ¿·¤ÎSDXC¤Þ¤ÇÌÖÍ夷¤Þ¤¹¡ª¡ª


¾ò·ï¤Ï°Ê²¼¤Î¤È¤ª¤ê¤È¤·¤Þ¤¹¡£
¡¦³Æ¥«¡¼¥É¤Ï¤¢¤é¤«¤¸¤áSDFormatter¤ÇFAT32¤Ç¥Õ¥©¡¼¥Þ¥Ã¥È¤¹¤ë¡£
¡¡64GB°Ê¾å¤ÎSDXC¤âHardDiskManager¤Ç̵Íý¤ä¤êFAT32¤Ç¥Õ¥©¡¼¥Þ¥Ã¥È¤·¤Þ¤¹¡£
¡¦¥×¥í¥°¥é¥à¤ÏSTM32F4ÈǤΤ¤¤Ä¤â¤Î¤Î3/31ÆüÈǤȤ·¤Þ¤¹¡£
¡¦»ÈÍѤ¹¤ë¥Ü¡¼¥É¤Ï180MHz¤ÇÆ°ºî²Äǽ¤ÊSTM32F427IIT6¤¬¾è¤Ã¤¿
¡¡STM32F4Á´Éô¾è¤»¥Ü¡¼¥É¤ò»ÈÍѤ·¤Þ¤¹¡£
¡¦SD¤Î¥¯¥í¥Ã¥¯¤Ï¥Ï¥¤¥¹¥Ô¡¼¥É¥â¡¼¥É¤È¤·¤Þ¤¹¡£¤³¤Î¥Ü¡¼¥É¤Ç¤Ï
¡¡SDIO_CLK¤ÎºÇ¹â¥¯¥í¥Ã¥¯¼þÇÈ¿ô¤Ï51.43MHz¤È¤Ê¤ê¤Þ¤¹¡£
¡¡¤Þ¤¿¡¢SDIO¤ÎžÁ÷¤Ë¤ÏDMA¤ò»ÈÍѤ·¤Þ¤¹¡£
¡¦Æɤ߽Ф·Â®ÅÙ¤Ï132949600Byte¤Î¥Õ¥¡¥¤¥ë¤Î¥·¡¼¥±¥ó¥·¥ã¥ëÆɤ߽Ф·¤Î®ÅÙ¤ò
¡¡Èæ³Ó¤·¤Þ¤¹(128MB¤ÎMMCv3¤ò½ü¤¯)¡£¤Þ¤¿¡¢¤Í¤à¤¤¤µ¤óŪ¤Ë¤ÏÆɤ߽Ф·¤·¤«¶½Ì£
¡¡¤Ê¤¤¤Î¤Ç½ñ¤­¹þ¤ßÈæ³Ó¤Ï¤ä¤ê¤Þ¤»¤ó¡£


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¡üToshibaÀ½eMMCv5 8GB

¤Þ¤º¤ÏÁ°²ó¤Î¤ª¤µ¤é¤¤¡¢ToshibaÀ½¤ÎeMMC8GB¤Ç¤¹¡£

FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 22961 kB/sec.
>ds 0
rc=0
Drive size: 15269888 sectors
Erase block size: 1024 sectors
Default r/w block size: 512 bytes
Card type: MMC(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 D0 5E 00 32 0F 59 03 FF FF FF FF EF 92 40 00 D3 .^.2.Y.......@..
CID:
00000000 11 01 00 30 30 38 47 45 30 00 5A DD 41 40 B2 0D ...008GE0.Z.A@..

Parsing MMC CID Register
Manufacturer ID :0x11
OEM/Application ID :<0>
Product Name :008GE0
Product Rev :0.0
Serial Number :0x5ADD4140
DateCode.Month :11
DateCode.Year :2015

Detected as MMCv5.0x Device!
OCR:
00000000 C0 FF 80 80 ....

Æɤ߽Ф·Â®ÅÙ¤¬22961kByte/Sec¤ÈSD¥«¡¼¥É¤òÍÞ¤¨¤Æ¥À¥ó¥È¥Ä¤ËÁᤤ¤Ç¤¹¡ª


¡üTranscendÀ½2GB MMCplus
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 22 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 21261 kB/sec.
>ds 0
rc=0
Drive size: 3939328 sectors
Erase block size: 256 sectors
Default r/w block size: 1024 bytes
Card type: MMC(Byte)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 90 2F 00 2A 1F 5A 83 C1 B6 DB 9F FF 96 80 00 3F ./.*.Z.........?
CID:
00000000 37 FF FF 4D 4D 43 30 32 47 10 F3 02 67 50 2C F5 7..MMC02G...gP,.

Parsing MMC CID Register
Manufacturer ID :0x37
OEM/Application ID :��
Product Name :MMC02G
Product Rev :1.0
Serial Number :0xF3026750
DateCode.Month :2
DateCode.Year :2009

Detected as MMCv4.0 Device!
OCR:
00000000 80 FF 80 80 ....

¤³¤Á¤é¤â¤Ê¤«¤Ê¤«¤Î¤ª¼êÁ°¤Ç¡£


¡üÆüËÜÀ½MMCv3¥«¡¼¥É
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fl
D---- 2016/03/14 23:28 0 .
D---- 2016/03/14 23:28 0 ..
----A 2010/03/13 20:06 44679600 ftbt.mp3
1 File(s), 44679600 bytes total
2 Dir(s), 83640320 bytes free
>fr 44679600
44679600 bytes read with 1904 kB/sec.
>ds 0
rc=0
Drive size: 250880 sectors
Erase block size: 32 sectors
Default r/w block size: 512 bytes
Card type: MMC(Byte)
SpeedMode: NomalSpeedMode(17.14MHz)
DataBusWidth: 1bit

CSD:
00000000 8C 26 01 2A 0F 59 81 E9 F6 DA 81 E3 9E 40 00 7D .&.*.Y.......@.}
CID:
00000000 11 00 00 30 31 32 38 4D 32 0A 05 80 FE CB 28 7D ...0128M2.....(}

Parsing MMC CID Register
Manufacturer ID :0x11
OEM/Application ID :<0><0>
Product Name :0128M2
Product Rev :0.10
Serial Number :0x0580FECB
DateCode.Month :2
DateCode.Year :2005

Detected as MMCv3.xx Card!
OCR:
00000000 80 FF 80 00 ....

MMCv3¤Ï20MHz°Ê²¼¤Î¥¯¥í¥Ã¥¯¤Ç¤Ê¤±¤ì¤Ð¤¤¤±¤Ê¤¤¤Î¤Ç¤½¤ì¤ò¼é¤Ã¤Æ¤¤¤Þ¤¹¡£
20MHz°Ê¾å¤Ç¤Ï³Î¤«¤ËÆ°ºî¤·¤Þ¤»¤ó¤Ç¤·¤¿¡£

¤³¤³¤«¤éÀè¤ÏSD¥«¡¼¥É¤Ç¤¹¡£


¡üTranscendÀ½x600¤ÎMicroSDHC8GB(TS8GUSDHC10U1)


ºòǯËö¤Ë¾Ò²ð¤·¤¿MLC¥¢¥Ô¡¼¥ë¤ÎÅۤǤ¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 22 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 20025 kB/sec.
>ds 0
rc=0
Drive size: 15759360 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 3C 1D 7F 80 0A 40 00 63 @..2[Y..<....@.c
CID:
00000000 74 4A 60 55 53 44 55 31 20 3B A1 5F AA 00 F6 25 tJ`USDU1 ;._...%

Parsing SD CID Register
Manufacturer ID :0x74
OEM/Application ID :J`
Product Name :USDU1
Product HwRev :2
Product SwRev :0
Serial Number :0x3BA15FAA
DateCode.Month :6
DateCode.Year :2015

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 03 00 00 00 04 00 90 00 08 11 39 00 ..............9.
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 03 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

·ë¹½Æɤ߽Ф·¤¬Áᤤ¤Ç¤¹¤Í¡£SD¥«¡¼¥É¤Ç¤Ï20000kB/Sec°Ê¾å¤À¤È
ÁᤤÉôÎà¤Ç¤¹¡£


¡üTranscendÀ½x600¤ÎSDHC32GB(TS32GSDHC10U1)

º£Å٤Ϥµ¤Ã¤­¤Î32GBÈÇ¡¢¤«¤ÄÄ̾掠¥¤¥º¤Î¤â¤Î¤Ç¤¹¡£
º£Ç¯½Õ¤Þ¤ÇTG-3¤Î»£±ÆÍѵ­Ï¿ÇÞÂΤȤ·¤Æ³èÌö¤·¤Æ¤¤¤Þ¤·¤¿¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 18130 kB/sec.
>ds 0
rc=0
Drive size: 63272960 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 F1 5D 7F 80 0A 40 00 79 @..2[Y...]...@.y
CID:
00000000 74 4A 60 53 44 55 31 20 20 46 F9 B9 1D 00 F5 67 tJ`SDU1 F.....g

Parsing SD CID Register
Manufacturer ID :0x74
OEM/Application ID :J`
Product Name :SDU1
Product HwRev :2
Product SwRev :0
Serial Number :0x46F9B91D
DateCode.Month :5
DateCode.Year :2015

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 05 00 00 00 04 00 90 00 08 11 39 00 ..............9.
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 03 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

¤Þ¤º¤Þ¤º¤Ç¤¹¤Í¡£


¡üTranscendÀ½MicroSDHC8GB

ÉáÄ̤ÎÎ÷²ÁÈǤÎÅۤǤ¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 15279 kB/sec.
>ds 0
rc=0
Drive size: 15456256 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 3A F5 7F 80 0A 40 00 43 @..2[Y..:....@.C
CID:
00000000 74 4A 45 55 53 44 55 31 02 05 B0 00 60 00 D1 E3 tJEUSDU1....`...

Parsing SD CID Register
Manufacturer ID :0x74
OEM/Application ID :JE
Product Name :USDU1
Product HwRev :0
Product SwRev :2
Serial Number :0x05B00060
DateCode.Month :1
DateCode.Year :2013

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 03 00 00 00 04 00 90 00 08 11 19 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 03 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

Î÷²ÁÈǤÀ¤±¤Ë®Å٤Ϥ½¤ì¤Ê¤ê¤Ç¤¹¡£


¡üSuperTalent MicroSDHC 4GB

¤ªÅ¹¤ÇƱÍÆÎÌÈæ¤ÇºÇ°ÂÃͤ˶ᤤÃÍÃʤÇÇ㤨¤¿SupterTalent¤ÎSD¥«¡¼¥É¤Ç¤¹¡£
¤¿¤·¤«780±ß¤Ç¤·¤¿¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 13677 kB/sec.
>ds 0
rc=0
Drive size: 7841792 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 1D E9 7F 80 0A 40 00 69 @..2[Y.......@.i
CID:
00000000 73 42 47 4E 43 61 72 64 10 19 23 6D 71 00 BB 81 sBGNCard..#mq...

Parsing SD CID Register
Manufacturer ID :0x73
OEM/Application ID :BG
Product Name :NCard
Product HwRev :1
Product SwRev :0
Serial Number :0x19236D71
DateCode.Month :11
DateCode.Year :2011

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 02 00 00 00 04 04 90 00 08 05 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 53 4D 49 00 00 00 00 .........SMI....
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

¥ê¡¼¥É¤¬13MB/SecŽ¥Ž¥Ž¥ŽÀŽÞŽÒŽÀŽÞŽÒ¤Ç¤¹¤Í¡£


¡üSuperTalent MicroSDXC64GB(FAT32 Format)

³¤¤¤Æ¤Ï64GBÈǤÎSDXC¤ÎÅۤǤ¹¡£¥Õ¥©¡¼¥Þ¥Ã¥È¤Ï̵Íý¤ä¤êFAT32¤Ç
¹Ô¤Ã¤¿¤¦¤¨¤Ç»î¤·¤Þ¤·¤¿¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 22 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 15772 kB/sec.
>ds 0
rc=0
Drive size: 125302784 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 01 DD FD 7F 80 0A 40 00 07 @..2[Y.......@..
CID:
00000000 28 42 45 20 20 20 20 20 02 00 33 3C 22 00 FA D3 (BE ..3<"...

Parsing SD CID Register
Manufacturer ID :0x28
OEM/Application ID :BE
Product Name :
Product HwRev :0
Product SwRev :2
Serial Number :0x00333C22
DateCode.Month :10
DateCode.Year :2015

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 08 00 00 00 04 00 90 00 08 11 19 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 45 80 03 00 00 00 00 .E......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :4
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDXC Card!

4GB¤ÎÅÛ¤è¤ê¥Þ¥·¤Ê¤â¤Î¤Î15MB/Sec¤Á¤ç¤Ã¤ÈŽ¥Ž¥¤ä¤Ã¤Ñ¤·¥À¥á¤Ç¤¹¤Í¡¦¡¦¡¦
¤Á¤Ê¤ß¤ËSCR¤ÎÃͤ¬¼¨¤¹¤È¤ª¤ê¤Á¤ã¤ó¤ÈSDXC¤È¤·¤Æǧ¼±¤Ç¤­¤Æ¤¤¤ë¤Î¤Ç
¥«¡¼¥É¤È¤·¤Æ¤Ï¤ì¤Ã¤­¤È¤·¤¿SDXC¤Ç¤¹¡£

SDHC¤ÈSDXC¤Î¸«Ê¬¤±Êý¤ÏÍÆÎ̤Τۤ«¤ËSCR¤ÎSD Security¤Î¥Ð¡¼¥¸¥ç¥ó¤«¤é
ʬÊ̤¹¤ë¤³¤È¤â²Äǽ¤Ç¤¹¡£


¡üKingMAX MicroSDHC32GB

¤³¤Á¤é¤âÎ÷²Á¤ÇÂؤ¨¤ë¥«¡¼¥É¤ÎɮƬ¤Ç¤¹¡£
Åö»þ¤Á¤ç¤Ã¤ÈÃͤ¬Ä¥¤Ã¤¿32GB¤òFatFs¤ÎÆ°ºî³ÎǧÍѤ˹ØÆþ¤·¤Æ¤¤¤Þ¤·¤¿¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 13668 kB/sec.
>ds 0
rc=0
Drive size: 62683136 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 EF 1D 7F 80 0A 40 00 27 @..2[Y.......@.'
CID:
00000000 13 4B 47 53 44 33 32 47 10 C2 00 51 1A 00 C7 A3 .KGSD32G...Q....

Parsing SD CID Register
Manufacturer ID :0x13
OEM/Application ID :KG
Product Name :SD32G
Product HwRev :1
Product SwRev :0
Serial Number :0xC200511A
DateCode.Month :7
DateCode.Year :2012

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 05 00 00 00 04 04 90 00 08 05 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

SuperTalent¤ÈƱ¤¸13MB/Sec...ŽÀŽÞŽÒŽÀŽÞŽºŽØŽ¬


¡üToshiba EXCERIA 16GB Type2¹ñÆâÀµµ¬ÈÇ

¤³¤Á¤é¤ÏTG-3¤Î¹ØÆþ¤ÈƱ»þ¤Ë¹ØÆþ¤·¤¿¹ñÆâ¤ÎÀµµ¬ÉʤǤ¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 21617 kB/sec.
>ds 0
rc=0
Drive size: 30867456 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 75 BF 7F 80 0A 40 00 93 @..2[Y..u....@..
CID:
00000000 02 54 4D 53 44 31 36 47 86 DE 58 C2 6E 00 E3 23 .TMSD16G..X.n..#

Parsing SD CID Register
Manufacturer ID :0x2
OEM/Application ID :TM
Product Name :SD16G
Product HwRev :8
Product SwRev :6
Serial Number :0xDE58C26E
DateCode.Month :3
DateCode.Year :2014

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 04 00 00 00 04 03 90 02 00 06 1A 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 B5 80 03 32 02 23 82 ....2.#.

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

20MB/Sec±Û¤¨¤Ç¤¹Ž¥Ž¥Ž¥¤ä¤Ã¤¿¤Í¡ù
ÃÍÃÊÄ¥¤Ã¤¿¹ÃÈ夬¤¢¤ê¤Þ¤·¤¿Ž¥Ž¥Ž¥


¡üToshiba EXCERIA MicroSDHC32GB ʹÔÍ¢ÆþÈÇ


º£ÅÙ¤ÏʹÔÍ¢ÆþÈǤÎÅۤǤ¹¡£¹â®¤Î¿®¹æ¤Î¤ä¤ê¼è¤ê¤ò°Õ¼±¤·¤Æ¤«
¤¤¤«¤Ê¤ëÊÑ´¹¥¢¥À¥×¥¿¡¼¤â»ÈÍÑÉԲĤȷٹ𤬤¢¤ê¤Þ¤·¤¿¡£¤Í¤à¤¤¤µ¤ó¤Î
»ÈÍÑË¡¤Ç¤Ï¹â¡¹50MHz¤Ý¤Ã¤Á¤Ê¤Î¤ÇÊ̤˴ط¸¤¢¤ê¤Þ¤»¤ó¤¬¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 22154 kB/sec.
>ds 0
rc=0
Drive size: 61079552 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 E8 FF 7F 80 0A 40 00 AF @..2[Y.......@..
CID:
00000000 02 54 4D 55 43 30 44 33 20 E9 C2 CF A5 00 EC 01 .TMUC0D3 .......

Parsing SD CID Register
Manufacturer ID :0x2
OEM/Application ID :TM
Product Name :UC0D3
Product HwRev :2
Product SwRev :0
Serial Number :0xE9C2CFA5
DateCode.Month :12
DateCode.Year :2014

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 05 00 00 00 02 02 90 02 00 06 3C 00 ..............<.
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 B5 84 03 32 02 29 02 ....2.).

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :1
SD Security :3
SD Bus Width :5

SD_Spec V4.xx!
Detected as SDHC Card!

¤ª¤ª¤Ã¡ªÅì¼Ç¤ÎeMMCv5¤ËɤŨ¤¹¤ë¥¹¥Ô¡¼¥É¤Ç¤¹¤è¤¥!!
¤³¤¤¤Ä¤Ï¥ª¥¹¥¹¥á¤Ç¤¹¡ù


¡üToshiba8GB MicroSDHC

Î÷²Á¤ÊÅì¼ÇÀ½¤ÎmicroSDHC¤Ç¤¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 20202 kB/sec.
>ds 0
rc=0
Drive size: 15564800 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 3B 5F 7F 80 0A 40 00 75 @..2[Y..;_...@.u
CID:
00000000 02 54 4D 53 44 30 38 47 56 C0 14 C0 4F 00 B1 C5 .TMSD08GV...O...

Parsing SD CID Register
Manufacturer ID :0x2
OEM/Application ID :TM
Product Name :SD08G
Product HwRev :5
Product SwRev :6
Serial Number :0xC014C04F
DateCode.Month :1
DateCode.Year :2011

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 03 00 00 00 04 03 90 08 00 F2 19 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 B5 80 03 28 03 51 02 ....(.Q.

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

¤³¤ì¤â¤Ê¤«¤Ê¤«¤Ç¤¹¤Í¡Á


¡üPanasonic 2GB MicroSD

380±ß¤Ç¤¿¤¿¤­Çä¤ê¤µ¤ì¤Æ¤¤¤¿MicroSD¤Ç¤¹¡£
STM32Primer2ÍѤ˹µ¤¨¤Ç¹ØÆþ¤·¤Æ¤¤¤Þ¤·¤¿¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 10776 kB/sec.
>ds 0
rc=0
Drive size: 3862528 sectors
Erase block size: 8192 sectors
Default r/w block size: 1024 bytes
Card type: SDv2(Byte)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 00 7F FF 32 5F 5A 83 AE F6 DB DF FF 8E 80 00 4B ...2_Z.........K
CID:
00000000 01 50 41 53 30 32 47 46 12 43 20 E0 52 00 B6 E1 .PAS02GF.C .R...

Parsing SD CID Register
Manufacturer ID :0x1
OEM/Application ID :PA
Product Name :S02GF
Product HwRev :1
Product SwRev :2
Serial Number :0x4320E052
DateCode.Month :6
DateCode.Year :2011

OCR:
00000000 80 FF 80 00 ....
SD Status:
00000000 80 00 00 00 00 00 00 28 02 02 90 00 10 05 00 00 .......(........
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 25 00 00 00 F0 02 10 .%......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :2
SD Bus Width :5

SD_Spec V2.00!
Detected as SDSC Card!

¤Þ¤¡¤³¤ó¤Ê¤â¤Î¤Ç¤¹¤ÍŽ¥Ž¥Ž¥


¡üPanasonic¤Î512MBSLC¶â¿§¥«¡¼¥É

¤³¤ì¤Ï¾¤ÎÅÛ¤é¤È¤Ï°ìÌ£°ã¤¤¤Þ¤¹¡ª¡ª¡ª
PanasonicÀ½¤Î¹©¶ÈÍÑSD¥«¡¼¥É¤Ç¤¹¡ª¡ª¡ª
¤½¤·¤ÆTLC¤¬Á´À¹¤Ë¤Ê¤Ã¤¿º£´õ¾¯¤ÊS¡¦L¡¦C!!!!
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 22 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 17939 kB/sec.
>ds 0
rc=0
Drive size: 967680 sectors
Erase block size: 4096 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Byte)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 00 0E 01 32 5B 59 81 D8 7F FF FF FF 12 40 00 FD ...2[Y.......@..
CID:
00000000 01 50 41 52 46 35 31 32 23 74 EF 95 6D 00 F6 B9 .PARF512#t..m...

Parsing SD CID Register
Manufacturer ID :0x1
OEM/Application ID :PA
Product Name :RF512
Product HwRev :2
Product SwRev :3
Serial Number :0x74EF956D
DateCode.Month :6
DateCode.Year :2015

OCR:
00000000 80 FF 80 00 ....
SD Status:
00000000 80 00 00 00 00 00 00 14 03 03 80 00 08 07 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 98 DC 90 26 76 16 08 ............&v..
00000020 01 00 93 02 41 12 22 00 00 00 00 00 00 00 00 40 ....A."........@
00000030 29 29 00 00 10 20 82 88 00 01 C6 00 00 00 17 1F ))... ..........
SCR:
00000000 02 A5 80 00 01 F0 01 01 ........

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :2
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDSC Card!

¤¢¤êŽ¥Ž¥Ž¥ÉáÄ̤ÀŽ¥Ž¥Ž¥¤Þ¡¢¤Þ¤¡¹©¶ÈÍѤǤ¹¤«¤é¥Ô¡¼¥­¡¼¤ÊÀ­Ç½¤è¤ê¤â
°ÂÄêÀ­¤È¤«Ž¿Ž¯ŽÁ¤Î¤Û¤¦¤¬¤¹¤´¤¤¤Î¤Ç¤·¤ç¤¦¤Í(»é´À)


¡ü̾¤â̵¤­16GB MicroSDHC

1078±ß¤Ç¤¿¤¿¤­Çä¤ê¤µ¤ì¤Æ¤¤¤¿MicroSDHC¤Ç¤¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 18257 kB/sec.
>ds 0
rc=0
Drive size: 31275008 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 77 4D 7F 80 0A 40 00 9D @..2[Y..wM...@..
CID:
00000000 28 42 45 48 30 33 30 39 10 00 00 19 C9 00 B1 ED (BEH0309........

Parsing SD CID Register
Manufacturer ID :0x28
OEM/Application ID :BE
Product Name :H0309
Product HwRev :1
Product SwRev :0
Serial Number :0x000019C9
DateCode.Month :1
DateCode.Year :2011

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 04 00 00 00 04 04 90 00 08 05 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 53 4D 49 00 00 00 00 .........SMI....
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

Ž¥Ž¥Ž¥¤¿¤¿¤­Çä¤ê¤Î¤¯¤»¤Ë¤ä¤ë¤¸¤ã¤Ê¤¤(ŽÆŽÔ


¡ü̾¤â̵¤­256MBMicroSD

¤³¤Á¤é¤Ï10ǯ°ÌÁ°¤Ë6800±ß¤Ç¹ØÆþ¤·¤¿¸Å¤Î256MB¤Î¥«¡¼¥É¤Ç¤¹¡£
¤Þ¤À¤Þ¤À¸½Ìò¥Ð¥ê¥Ð¥ê¤Ê¤Î¤Ç¤¹¤è¤¥
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 12321 kB/sec.
>ds 0
rc=0
Drive size: 499712 sectors
Erase block size: 128 sectors
Default r/w block size: 512 bytes
Card type: SDv1
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 00 5E 00 32 57 59 83 CF ED B6 FF 87 96 40 00 D3 .^.2WY.......@..
CID:
00000000 4B 46 4D 53 44 20 20 20 10 03 00 25 63 00 69 7D KFMSD ...%c.i}

Parsing SD CID Register
Manufacturer ID :0x4B
OEM/Application ID :FM
Product Name :SD
Product HwRev :1
Product SwRev :0
Serial Number :0x03002563
DateCode.Month :9
DateCode.Year :2006

OCR:
00000000 80 FF 80 00 ....
SD Status:
00000000 80 00 00 00 00 00 00 28 00 00 00 00 00 00 00 00 .......(........
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 01 25 00 00 00 00 00 00 .%......

Parsing SCR
SD Spec Version :1
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :2
SD Bus Width :5

SD_Spec V1.10!
Detected as SDSC Card!

ÂçÀΤΥ«¡¼¥É¤Ê¤Î¤ÇSD¤Î¥Ð¡¼¥¸¥ç¥ó¤Ï1.10¤Ç¤¹¡£
¤³¤Î¥«¡¼¥É¤ÏBIOS¤Î¹¹¿·ÍÑ¥Ö¡¼¥È¥á¥â¥ê¤È¤·¤ÆUSB¥«¡¼¥É¥ê¡¼¥À¤È
ÁȤ߹ç¤ï¤»¤Æº£¤Ç¤â»ÈÍѤ·¤Æ¤ª¤ê¤Þ¤¹¡£


¡üRiDATA 256MB MiniSD

¤½¤·¤Æ¹¹¤ËÀΤÎ11ǯÁ°¤ËMP3¥×¥ì¡¼¥ä¡¼ÍѤ˹ØÆþ¤·¤¿MiniSD¤Î¥«¡¼¥É¤Ç¤¹¡ª
³Î¤«9870±ß¤¯¤é¤¤¤ÇÇã¤Ã¤¿¤È»×¤¤¤Þ¤·¤¿¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 7666 kB/sec.
>ds 0
rc=0
Drive size: 492544 sectors
Erase block size: 128 sectors
Default r/w block size: 512 bytes
Card type: SDv1
SpeedMode: NomalSpeedMode(25.72MHz)
DataBusWidth: 4bit

CSD:
00000000 00 7F 00 32 13 59 81 E0 EE BB 3F FF 16 40 00 E9 ...2.Y....?..@..
CID:
00000000 04 00 00 53 44 00 00 2A 10 00 00 03 3A 00 48 97 ...SD..*....:.H.

Parsing SD CID Register
Manufacturer ID :0x4
OEM/Application ID :<0><0>
Product Name :SD<0><0>*
Product HwRev :1
Product SwRev :0
Serial Number :0x0000033A
DateCode.Month :8
DateCode.Year :2004

OCR:
00000000 80 FF 80 00 ....
SD Status:
00000000 80 00 00 00 00 00 00 14 00 00 00 00 00 00 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 00 A5 00 00 00 00 00 00 ........

Parsing SCR
SD Spec Version :0
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :2
SD Bus Width :5

SD_Spec V1.0x!
Detected as SDSC Card!

¤Ê¤ó¤ÈSD¤Î¥Ð¡¼¥¸¥ç¥ó¤ÏHighSpeedMode¤Ë¤¹¤éÂбþ¤·¤Æ¤¤¤Ê¤¤V1.0¤Ç¤¹Ž¥Ž¥Ž¥
»ä¤¬»ý¤ÄºÇ¸Å¤ÎSD¥«¡¼¥É¤Ç¤¹¡£


¡üATP ProMAX MiniSD 1GB x150

¤Í¤à¤¤¤µ¤ó¥¤¥Á¥ª¥·¤Î¥á¡¼¥«¡¼ATPÀ½¤Î¥«¡¼¥É¤Ç¤¹¡£
¤³¤Á¤é¤ÏÈ¢¤ËSLC¤ÈÌÀµ­¤µ¤ì¤Æ¤ª¤ê¤Þ¤·¤¿¡£15000±ß¤¯¤é¤¤¤Ç¥è¥É¥Ð¥·¤Ç
Çã¤Ã¤¿µ­²±¤¬¤¢¤ê¤Þ¤¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 19499 kB/sec.
>ds 0
rc=0
Drive size: 1999872 sectors
Erase block size: 128 sectors
Default r/w block size: 512 bytes
Card type: SDv1
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 00 5E 00 32 5F 59 83 D0 6D B7 FF 9F 96 40 00 8F .^.2_Y..m....@..
CID:
00000000 09 41 50 41 46 4D 44 50 10 45 30 00 C2 00 63 DD .APAFMDP.E0...c.

Parsing SD CID Register
Manufacturer ID :0x9
OEM/Application ID :AP
Product Name :AFMDP
Product HwRev :1
Product SwRev :0
Serial Number :0x453000C2
DateCode.Month :3
DateCode.Year :2006

OCR:
00000000 80 FF 80 00 ....
SD Status:
00000000 80 00 00 00 00 00 00 38 00 00 00 00 00 00 00 00 .......8........
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 01 25 00 00 00 00 00 00 .%......

Parsing SCR
SD Spec Version :1
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :2
SD Bus Width :5

SD_Spec V1.10!
Detected as SDSC Card!

¤ä¤ê¤Þ¤¹¤Í¡Á¡ª


¡üATP MicroSDHC4GB MLC (AF4GUD-ATP023)

¤³¤Á¤é¤ÏSTM32F4¤Î¤¤¤Ä¤â¤Î¤Ç»ÈÍѤ·¤Æ¤¤¤ë¤ª¤Ê¤¸¤ß¤ÎATP¤ÎMicroSDHC¤Ç¤¹¡£
°ìÈÌÍѤʤΤÇMLC¤Ç¤¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 22 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 21173 kB/sec.
>ds 0
rc=0
Drive size: 7861248 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5F 59 00 00 1D FC 7F 80 0A 40 00 97 @..2_Y.......@..
CID:
00000000 09 41 50 41 46 20 55 44 10 26 3B 15 32 00 83 A5 .APAF UD.&;.2...

Parsing SD CID Register
Manufacturer ID :0x9
OEM/Application ID :AP
Product Name :AF UD
Product HwRev :1
Product SwRev :0
Serial Number :0x263B1532
DateCode.Month :3
DateCode.Year :2008

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 02 00 00 00 03 03 90 00 08 05 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 00 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V2.00!
Detected as SDHC Card!

®ÅÙ¤âʸ¶ç¤Ê¤·¡ª


¡üATP MicroSDHC4GB SLC (AF4GUDI-5ABXX)

¤½¤·¤ÆƱ¤¸ATP¤Î¹©¶ÈÍѤÎMicroSDHC¤Ç¤¹¡ª¡ª¡ª¡ª¡ª
¤â¤Á¤í¤óSLC¤Ê¤Î¤Ç¤¹¤è¤¥¡ª¼ÂÎϤ䤤¤«¤Ë¡ª¡©
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 22 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 16330 kB/sec.
>ds 0
rc=0
Drive size: 7892992 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 1E 1B 7F 80 0A 40 00 B1 @..2[Y.......@..
CID:
00000000 09 41 50 41 46 20 55 44 10 12 60 75 7A 00 F2 39 .APAF UD..`uz..9

Parsing SD CID Register
Manufacturer ID :0x9
OEM/Application ID :AP
Product Name :AF UD
Product HwRev :1
Product SwRev :0
Serial Number :0x1260757A
DateCode.Month :2
DateCode.Year :2015

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 02 00 00 00 03 03 90 00 08 05 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 00 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V2.00!
Detected as SDHC Card!

¤¡Ž¥Ž¥Ž¥¤¢¤ìŽ¥Ž¥Ž¥¡©¤Þ¡¢¤Þ¤¡¹©¶ÈÍѤǤ¹¤«¤é¥Ô¡¼¥­¡¼¤Ê
À­Ç½¤è¤ê¤â°ÂÄêÀ­¤ò¶¯²½¤·¤Æ¤¤¤ë¤Î¤Ç¤·¤ç¤¦(»é´À)
Âç»ö¤Ê»ö¤Ê¤Î¤ÇÆóÅÙ¸À¤¤¤Þ¤·¤¿¡£


¡üSandisk Ultra8GB MicroSDHC

¥È¥ê¤ÏSanDisk¤ÎSD¥«¡¼¥É¤¿¤Á¤Ç¤¹¡ª
µ¶¼Ô¤¬ÍðÉñ¤¹¤ëSandiskÀ½¤Ç¤¹¤¬¤Í¤à¤¤¤µ¤ó¤¤¤Á¤ª¤¦¤Á¤ã¤ó¤È¤·¤¿¤ªÅ¹¤Ç
Çã¤Ã¤Æ¤¤¤ë¤Î¤Çµ¶¼Ô¤Ë¤Ï°ú¤Ã¤«¤«¤Ã¤Æ¤ª¤ê¤Þ¤»¤óŽ¥Ž¥Ž¥¤Ï¤ºŽ¥Ž¥Ž¥
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 16421 kB/sec.
>ds 0
rc=0
Drive size: 15523840 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 3B 37 7F 80 0A 40 40 AF @..2[Y..;7...@@.
CID:
00000000 03 53 44 53 55 30 38 47 80 02 37 95 01 00 C6 87 .SDSU08G..7.....

Parsing SD CID Register
Manufacturer ID :0x3
OEM/Application ID :SD
Product Name :SU08G
Product HwRev :8
Product SwRev :0
Serial Number :0x02379501
DateCode.Month :6
DateCode.Year :2012

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 03 00 00 00 04 00 90 00 14 05 1A 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 80 01 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

¤Õ¤Ä¡¼Ž¥Ž¥Ž¥


¡üSandisk Ultra­¶ 8GB SDHC

¤³¤Î¥«¡¼¥É¤Ï¤ª¿¬¤ËUSB¤Îü»Ò¤¬ÉÕ¤¤¤Æ¤¤¤ÆUSB¥á¥â¥ê¤È¤·¤Æ¤âµ¡Ç½¤·¤Þ¤¹¡£
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Apr 3 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 14268 kB/sec.
>ds 0
rc=0
Drive size: 15954944 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 3C DC 7F 80 0A 40 40 C5 @..2[Y..<....@@.
CID:
00000000 03 53 44 53 44 30 38 47 80 01 9C 01 36 00 84 65 .SDSD08G....6..e

Parsing SD CID Register
Manufacturer ID :0x3
OEM/Application ID :SD
Product Name :SD08G
Product HwRev :8
Product SwRev :0
Serial Number :0x019C0136
DateCode.Month :4
DateCode.Year :2008

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 03 00 00 00 02 02 90 00 0B 05 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 35 00 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :0
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V2.00!
Detected as SDHC Card!

µ¡Ç½À¹¤ê¹þ¤ß¤¹¤®¤Æ¤Á¤ç¤Ã¤È®ÅÙ¤¬ÃÙ¤¤¤Ç¤¹¤¬¤·¤«¤¿¤Ï̵¤¤¤Ç¤¹¡£


¡üSandisk ExtremePRO SDXC64GB(FAT32¥Õ¥©¡¼¥Þ¥Ã¥È)

¤½¤·¤Æ¡ª¸½ºßTG-3ÍѤε­²±ÇÞÂΤȤ·¤Æ¥Ð¥ê¥Ð¥ê¤Ë»È¤Ã¤Æ¤¤¤Þ¤¹ExtremePRO¤Î
64GB¤Î¥«¡¼¥É¤Ç¤¹¡ª¡ª¡ª
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 25 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 16448 kB/sec.
>ds 0
rc=0
Drive size: 124735488 sectors
Erase block size: 32768 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 01 DB D3 7F 80 0A 40 40 DF @..2[Y.......@@.
CID:
00000000 03 53 44 53 50 36 34 47 80 F2 D6 14 07 01 01 D5 .SDSP64G........

Parsing SD CID Register
Manufacturer ID :0x3
OEM/Application ID :SD
Product Name :SP64G
Product HwRev :8
Product SwRev :0
Serial Number :0xF2D61407
DateCode.Month :1
DateCode.Year :2016

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 08 00 00 00 04 00 C0 00 0F 05 3A 00 ..............:.
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
SCR:
00000000 02 45 84 03 00 00 00 00 .E......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :1
SD Security :4
SD Bus Width :5

SD_Spec V4.xx!
Detected as SDXC Card!

¤¢¤ê¤ã¤ê¤ãŽ¥Ž¥Ž¥
¤ÞŽ¥Ž¥¤Þ¤¡Ž¥Ž¥Ž¥FAT32¤Ç̵Íýʵ¥Õ¥©¡¼¥Þ¥Ã¥È¤·¤Æ¤Þ¤¹¤·¤½¤Î¤»¤¤¤Ç¤·¤ç¤¦(»é´À)
¥«¡¼¥É¤ÎŽÓŽÉ¤È¤·¤Æ¤ÏSD¤Î¥Ð¡¼¥¸¥ç¥ó¤â4¤ÎºÇ¿·¤Î¤ä¤Ä¤Ç¤¹¡£
º£²ó¤Îɾ²Á¤ÇSD¥Ð¡¼¥¸¥ç¥ó¤¬4¤ÎÅۤϤ³¤ì¤ÈʹÔÍ¢ÆþÈÇEXCERIA¤À¤±¤Ç¤·¤¿¡£
¤É¤¦¤Ç¤â¤¤¤¤¤Ç¤¹¤±¤Éeraseblocksize¤¬32768¥»¥¯¥¿¤â¤¢¤ê¤Þ¤¹¡£


¡üI/OData¤ÎClass4 SDHC4GB

¤Í¤à¤¤¤µ¤ó¤Î¤ª¤È¤¦¤Á¤ã¤ó¤«¤éŽ¢¤ªÁ°¤¬»³¤Ë¹Ô¤Ã¤¿»þ¤Î¼Ì¿¿Ê¬¤±¤Æ¤¯¤ìŽ£¤È
Íê¤Þ¤ì¼êÅϤµ¤ì¤¿¤É¤Ã¤«¤Î²ÈÅÅÎÌÈÎŹ¤ÇÇã¤Ã¤Æ¤­¤¿¤«¤Î¤è¤¦¤Ê¥Ç¡¼¥¿ÊݸÍѤÎ
¤ä¤Ã¤¹¤¤¥«¡¼¥É¤Ç¤¹¡£¤É¤¦¤»¥´¥ß¤ß¤¿¤¤¤ÊÀ­Ç½¤À¤í¤¦¤«¤éÓ¢¤Ã¤Æ¤ä¤ë¤Ä¤â¤ê¤Ç
Ⱦ¤ÐÎä¤ä¤«¤·¤Ë¥Ù¥ó¥Á¤È¤Ã¤Æ¤ß¤¿¤Î¤Ç¤¹¤¬Ž¥Ž¥Ž¥
FatFs module test terminal for STM32F427IIT6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 25 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 19063 kB/sec.
>ds 0
rc=0
Drive size: 7878656 sectors
Erase block size: 8192 sectors
Default r/w block size: 512 bytes
Card type: SDv2(Block)
SpeedMode: HighSpeedMode(51.43MHz)
DataBusWidth: 4bit

CSD:
00000000 40 0E 00 32 5B 59 00 00 1E 0D 7F 80 0A 40 00 A5 @..2[Y.......@..
CID:
00000000 1D 41 44 53 44 20 20 20 10 A0 90 08 0A 00 02 E3 .ADSD ........

Parsing SD CID Register
Manufacturer ID :0x1D
OEM/Application ID :AD
Product Name :SD
Product HwRev :1
Product SwRev :0
Serial Number :0xA090080A
DateCode.Month :2
DateCode.Year :2000

OCR:
00000000 C0 FF 80 00 ....
SD Status:
00000000 80 00 00 00 02 00 00 00 02 02 90 00 08 11 00 00 ................
00000010 00 00 00 00 00 00 00 00 00 53 4D 49 00 00 00 00 .........SMI....
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00000030 00 00 00 51 00 00 00 00 32 00 00 00 00 00 00 00 ...Q....2.......
SCR:
00000000 02 35 80 00 00 00 00 00 .5......

Parsing SCR
SD Spec Version :2
SD Spec Version 3 :1
SD Spec Version 4 :0
SD Security :3
SD Bus Width :5

SD_Spec V3.0x!
Detected as SDHC Card!

>132949600 bytes read with 19063 kB/sec.
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STM32F4¤ÎÈĤ˺¹¤·¤ÆÈ¿±þ¸«¤Æ¤ß¤ë¤«¤È»×¤Ã¤¿¤é¤Ê¤ó¤ÈÉáÄ̤Ëǧ¼±¤·¤Æ¤·¤Þ¤Ã¤¿¡Ä¡£
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¤§¤Ã¡ª¡©¹õß·¥À¥¤¥ä¤Á¤ã¤ó¤Î¤ª¸ý¤¬Ž²Ž¹ŽÅŽ²¤³¤È¤Ë¤Ê¤Ã¤Æ¤ë¤Ã¤Æ¡ª¡©²¿¤Î¤³¤È¤ä¤éŽÊŽÊ
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¤¹¤ë¤¿¤á¤ÎÆÃÊ̤ʥ³¥Þ¥ó¥É·²¤Ï»ÈÍѤ·¤Æ¤ª¤é¤º¡¢SDHC/SDXC¤ÈƱ¤¸´¶³Ð¤ÇÆɤß
½ñ¤­¤·¤Þ¤¹¡£ÏӤ˼«¿®¤¬¤¢¤ë¿Í¡¢»ä¤Î¥³¡¼¥É¤ò»²¹Í¤Ë³ÈÄ¥¤·¤Æ¤¯¤À¤µ¤¤Ž¥Ž¥Ž¥(º©´ê)



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>ds 0
rc=0
Drive size: 15269888 sectors
Erase block size: 1024 sectors
Default r/w block size: 512 bytes
Card type: MMC(Block)
CSD:
00000000 D0 5E 00 32 0F 59 03 FF FF FF FF EF 92 40 00 D3 .^.2.Y.......@..
CID:
00000000 11 01 00 30 30 38 47 45 30 00 5A DD 41 40 B2 0D ...008GE0.Z.A@..

Parsing MMC CID Register
Manufacturer ID :0x11
OEM/Application ID :<0>
Product Name :008GE0
Product Rev :0.0
Serial Number :0x5ADD4140
DateCode.Month :11
DateCode.Year :1999

Detected as MMCv5.0x Device!
OCR:
00000000 C0 FF 80 80 ....
Á°²ó½Ò¤Ù¤¿¤È¤ª¤êMMCv4.xx°Ê¹ß¤ÏExtCSD¥ì¥¸¥¹¥¿¤òÆɤ߽Ф¹¤Î¤Ï½ÅÍפǤ¹¡£
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ExtCSDREV¤Ï¡É7¡É¤È¤Ê¤ê¤Á¤ã¤ó¤Èv5¤Î¥Ç¥Ð¥¤¥¹¤Ç¤¢¤ë¤³¤È¤¬Ê¬¤«¤ê¤Þ¤¹¡£
¤Á¤Ê¤ß¤Ëdatecode¤¬1999¤È¤¢¤ë¤Î¤ÏCID¥ì¥¸¥¹¥¿¤Îǯ¿ô¤ò¼¨¤¹¥Õ¥£¡¼¥ë¥É¤¬4bitʬ
¤·¤«¤Ê¤¤¤Î¤Ç2012ǯ¤ò¶­¤Ëǯ¿ô¤¬°ì½ä¤·¤Æ¤·¤Þ¤Ã¤Æ¤¤¤ë¤«¤é¤Ç¤¹¡£ºÇ¿·¤ÎMMCA¤Î
¥Ç¡¼¥¿¥·¡¼¥È¤Ç¤ÏExtCSDREV¤«¤é2012ǯ°Ê¹ß¤òȽÊ̤»¤è¤È¤¤¤¦¤è¤¦¤Ë¤Ê¤Ã¤Æ¤¤¤Þ¤¹¤Î¤Ç
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FatFs module test terminal for STM32F746NGH6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 31 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 22000 kB/sec.
>
¥·¡¼¥±¥ó¥·¥ã¥ë¥é¥¤¥È¤â¸«¤Æ¤ß¤Þ¤·¤¿¡£F7¤Î¥µ¥ó¥×¥ë¤Ç¤ÏSDIO_CLK¤ÏMAX48MHz
¤«¤Ä4bit¥â¡¼¥É¤ÎÀßÄ꤬eMMC¤Ç²Äǽ¤Ç¤¹¤¬¤´Í÷¤Î¤È¤ª¤êÍýÏÀÃͤ˶ᤤÆɤ߽Ф·
®ÅÙ¤¬½Ð¤Þ¤·¤¿¡£¤ä¤ë¤¸¤ã¤Ê¤¤¡ª
FatFs module test terminal for STM32F746NGH6
LFN Enabled, Code page: 932
AppVersion : W.I.P
Build Date : Mar 31 2016
>fg piano
rc=0 FR_OK
>fo 1 ftbt.mp3
rc=0 FR_OK
>fr 132949600
132949600 bytes read with 20753 kB/sec.
>
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¤³¤È¤¬½ÐÍè¤ë¤è¤¦¤Ë¤Ê¤ê¤Þ¤·¤¿¡ªº£½©¤¯¤é¤¤¤Ë»Ô¾ì¤Ë½Ð²ó¤ë¤Ç¤¢¤í¤¦STM32F777Åù¤Î
ºÇ¶¯¤Ë¶¯¤Þ¤Ã¤¿F7¥·¥ê¡¼¥º¤Ç¤ÏSDMMC¤¬Æó¤Ä¤ËÁý¤¨¤ë¤Î¤Ç´ðÈÄÉÕ¤±ÃÖ¤­¤ÎeMMC
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¤Î¤Ç¤É¤ó¤É¤ó»î¤·¤Æ²¼¤µ¤¤¡ª¤Ä¤¤¤Ç¤Ë¥Ð¥°¤â¤³¤Ã¤½¤ê¶µ¤¨¤Æ¤â¤é¤¨¤ë¤È½õ¤«¤ê¤Þ¤¹¡ù

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¤è¤¦¤Ë¤Ê¤Ã¤¿¤Î¤Ç¤·¤ç¤¦¤«¡Ä???º£²ó¤Ï¤Á¤ç¤Ã¤È¾Ð¤¨¤¿¤Î¤Çµö¤·¤Þ¤¹¤¬¡£
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¤Î¤ÇÃפ·Êý¤Ê¤·¤Ç¤¹¡£¥«¡¼¥É¤È¤·¤ÆÀµ¤·¤¯Æ°ºî¤¹¤ì¤ÐOK¤Ç¤¹¡£


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STM32CubeHAL¥é¥¤¥Ö¥é¥ê¤ËMMC¤Î¥µ¥Ý¡¼¥È¤ÏÁ´¤¯Í­¤ê¤Þ¤»¤ó¡£¤½¤ì¤É¤³¤í¤«¤Ê¤ó¤È
²áµî¤ÎSPL¤Ë¤ÏÂбþ¤·¤Æ¤¤¤¿SDv1.xx·Ï¥«¡¼¥É¤Î¥µ¥Ý¡¼¥È¤¹¤é¤âHAL¥é¥¤¥Ö¥é¥ê¤Ç¤Ï
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>ds 0
rc=0
Drive size: 3939328 sectors
Erase block size: 256 sectors
Default r/w block size: 1024 bytes
Card type: MMC(Byte)

CSD:
00000000 90 2F 00 2A 1F 5A 83 C1 B6 DB 9F FF 96 80 00 3F ./.*.Z.........?
CID:
00000000 37 FF FF 4D 4D 43 30 32 47 10 F3 02 67 50 2C F5 7..MMC02G...gP,.

Parsing MMC CID Register
Manufacturer ID :0x37
OEM/Application ID :
Product Name :MMC02G
Product Rev :1.0
Serial Number :0xF3026750
DateCode.Month :2
DateCode.Year :2009

Detected as MMCv4.0 Device!
OCR:
00000000 80 FF 80 80 ....

¡ü128MB MMCv3
>ds 0
rc=0
Drive size: 250880 sectors
Erase block size: 32 sectors
Default r/w block size: 512 bytes
Card type: MMC(Byte)
CSD:
00000000 8C 26 01 2A 0F 59 81 E9 F6 DA 81 E3 9E 40 00 7D .&.*.Y.......@.}
CID:
00000000 11 00 00 30 31 32 38 4D 32 0A 05 80 FE CB 28 7D ...0128M2.....(}

Parsing MMC CID Register
Manufacturer ID :0x11
OEM/Application ID :<0><0>
Product Name :0128M2
Product Rev :0.10
Serial Number :0x0580FECB
DateCode.Month :2
DateCode.Year :2005

Detected as MMCv3.xx Device!
OCR:
00000000 80 FF 80 00 ....
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uint64_t unk0;
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ext_csd.EXT_CSD.SEC_COUNT[2] << 16 | ¥
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ext_csd.EXT_CSD.SEC_COUNT[2] << 16 | ¥
ext_csd.EXT_CSD.SEC_COUNT[1] << 8 | ¥
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> "C:¥Devz¥Coreutils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f target/stm32f7discovery_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.10.0-dev-00104-gf3be0f6-dirty (2015-11-13-09:52)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v24 API v2 SWIM v11 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.219974
Info : stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints
stm32f7x.cpu: target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0803276c msp: 0x20010000
auto erase enabled
Info : device id = 0x10016449
Info : flash size = 1024kbytes
stm32f7x.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000046 msp: 0x20010000
wrote 786432 bytes from file main.elf in 18.501879s (41.509 KiB/s)
stm32f7x.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20010000
stm32f7x.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20010000
stm32f7x.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20010000
verified 600552 bytes in 2.451303s (239.251 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:21

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inline void Display_wr_block_if(uint8_t *p,unsigned int cnt)
{
/* Set Display Pointer */
lcd_c_buf_ptr = lcd_f_buf_ptr + 2*(lcdc.x + MAX_X*lcdc.y);

/* configure DMA2D */
DMA2D_DeInit();
DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M_PFC;
DMA2D_InitStruct.DMA2D_OutputMemoryAdd = (uint32_t)lcd_c_buf_ptr;
DMA2D_InitStruct.DMA2D_OutputOffset = (MAX_X - ((lcdc.width+1) - lcdc.x));
DMA2D_InitStruct.DMA2D_NumberOfLine = (lcdc.height+1) -lcdc.y;
DMA2D_InitStruct.DMA2D_PixelPerLine = (lcdc.width+1) -lcdc.x;
DMA2D_Init(&DMA2D_InitStruct);

/* Configure default values for foreground */
DMA2D_FG_StructInit(&DMA2D_FG_InitStruct);
DMA2D_FG_InitStruct.DMA2D_FGMA = (uint32_t)p;
DMA2D_FGConfig(&DMA2D_FG_InitStruct);

/* Start Transfer */
DMA2D_StartTransfer();

/* Wait for CTC Flag activation */
while(DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET){}
}

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inline void Display_wr_block_if(uint8_t *p,unsigned int cnt)
{
/* Set Display Pointer */
lcd_c_buf_ptr = lcd_f_buf_ptr + 2*(lcdc.x + MAX_X*lcdc.y);

/* configure DMA2D */
Dma2dHandle.Init.Mode = DMA2D_M2M_PFC; /* memory to memory with PFC */
Dma2dHandle.Init.OutputOffset = (MAX_X - ((lcdc.width+1) - lcdc.x));
/* DMA2D Initialisation */
if(HAL_DMA2D_Init(&Dma2dHandle) != HAL_OK)
{
/* Initialization Error */
while(1);
}

/*¡¡Start DMA2D transfer */
if(HAL_DMA2D_Start_IT(&Dma2dHandle,
/* Source Buffer */
(uint32_t)p,
/* Dist Buffer */
(uint32_t)lcd_c_buf_ptr,
/* width in pixels */
((lcdc.width+1) -lcdc.x),
/* height in pixels */
((lcdc.height+1) -lcdc.y))
!= HAL_OK)
{
/* Initialization Error */
while(1);
}
}

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/* If unligned memory address situation,copy dmabuf to aligned by 4-Byte. */
/* SECTOR_SIZE = 512 (Byte) */
uint8_t dmabuf[SECTOR_SIZE] __attribute__ ((aligned (4)));

if((uint32_t)buff & 3)	/* Check 4-Byte Alignment */
{ /* Unaligned Buffer Address Case (Slower) */
for (unsigned int secNum = 0; secNum < count && Status == SD_OK; secNum++){
/* Use optimized memcpy for ARMv7-M, std memcpy was override by optimized one. */
memcpy(dmabuf, buff+SECTOR_SIZE*secNum, SECTOR_SIZE);
Status = SD_WriteBlock(dmabuf,
(uint64_t)(sector+secNum)*SECTOR_SIZE,
(uint8_t)SECTOR_SIZE);
}
} else {
/* Aligned Buffer Address Case (Faster) */
if(count==1){
Status = SD_WriteBlock((uint8_t*)(buff),
((uint64_t)(sector)*SECTOR_SIZE),
SECTOR_SIZE);
}
else{
Status = SD_WriteMultiBlocks((uint8_t*)(buff),
((uint64_t)(sector)*SECTOR_SIZE),
SECTOR_SIZE
,count);
}
}

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SD_Error SD_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
SD_Error errorstatus = SD_OK;

/* SDIO Peripheral Low Level Init */
/* GPIOC and GPIOD Periph clock enable */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE);

GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO);

/* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOC, &GPIO_InitStructure);

/* Configure PD.02 CMD line */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_Init(GPIOD, &GPIO_InitStructure);

/* Configure PC.12 pin: CLK pin */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOC, &GPIO_InitStructure);

/*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
#ifdef SDIO_INS_DETECT
GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
#endif

/*
*NVIC_PriorityGroup_0: 0 Pre-emption priorities, 16 Sub-priorities
*NVIC_PriorityGroup_1: 2 Pre-emption priorities, 8 Sub-priorities
*NVIC_PriorityGroup_2: 4 Pre-emption priorities, 4 Sub-priorities
*NVIC_PriorityGroup_3: 8 Pre-emption priorities, 2 Sub-priorities
*NVIC_PriorityGroup_4: 16 Pre-emption priorities, 0 Sub-priorities
*/
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);

/* Enable the SDIO Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_Init(&NVIC_InitStructure);

/* Enable the SDIO APB2 Clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE);

#if defined(SD_DMA_MODE)
/* Enable the DMA Clock */
RCC_AHB1PeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE);
/* Initialize SDDMA Structure */
SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL;
SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
SDDMA_InitStructure.DMA_Memory0BaseAddr = 0;
SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
SDDMA_InitStructure.DMA_BufferSize = 0;
SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;
#endif
/* End of LowLevel Init */


SDIO_DeInit();

errorstatus = SD_PowerON();

if (errorstatus != SD_OK)
{
/*!< CMD Response TimeOut (wait for CMDSENT flag) */
return(errorstatus);
}

errorstatus = SD_InitializeCards();

if (errorstatus != SD_OK)
{
/*!< CMD Response TimeOut (wait for CMDSENT flag) */
return(errorstatus);
}

/*!< Configure the SDIO peripheral */
/*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV) */
/*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */
SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
SDIO_Init(&SDIO_InitStructure);

/*----------------- Read CSD/CID MSD registers ------------------*/
if (errorstatus == SD_OK)
{
errorstatus = SD_GetCardInfo(&SDCardInfo);
}

/*----------------- Select Card --------------------------------*/
if (errorstatus == SD_OK)
{
errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16));
}

/*----------------- Enable SDC 4BitMode --------------------------------*/
if (errorstatus == SD_OK)
{
errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b);
}

#ifdef SD_HS_MODE
/*----------------- Enable HighSpeedMode --------------------------------*/
#warning "Enable SD High Speed mode!"
if (errorstatus == SD_OK)
{
errorstatus = SD_HighSpeed();
}
#endif

return(errorstatus);
}

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SD_Error SD_HighSpeed (void)
{
SD_Error errorstatus = SD_OK;
uint32_t scr[2] = {0, 0};
uint32_t SD_SPEC = 0 ;
uint8_t hs[64] = {0} ;
uint32_t count = 0, *tempbuff = (uint32_t *)hs;
TransferError = SD_OK;
TransferEnd = 0;
StopCondition = 0;

SDIO->DCTRL = 0x0;

/*!< Get SCR Register */
errorstatus = FindSCR(RCA, scr);

if (errorstatus != SD_OK)
{
return(errorstatus);
}

/* Test the Version supported by the card*/
SD_SPEC = (scr[1] & 0x01000000)||(scr[1] & 0x02000000);

if (SD_SPEC != SD_ALLZERO)
{
/* Set Block Size for Card */
SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)64;
SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
SDIO_SendCommand(&SDIO_CmdInitStructure);
errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
if (errorstatus != SD_OK)
{
return(errorstatus);
}
SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
SDIO_DataInitStructure.SDIO_DataLength = 64;
SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b ;
SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
SDIO_DataConfig(&SDIO_DataInitStructure);

/*!< Send CMD6 switch mode */
SDIO_CmdInitStructure.SDIO_Argument = 0x80FFFF01;
SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_HS_SWITCH;
SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
SDIO_SendCommand(&SDIO_CmdInitStructure);
errorstatus = CmdResp1Error(SD_CMD_HS_SWITCH);

if (errorstatus != SD_OK)
{
return(errorstatus);
}
while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
{
if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
{
for (count = 0; count < 8; count++)
{
*(tempbuff + count) = SDIO_ReadData();
}
tempbuff += 8;
}
}

if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
errorstatus = SD_DATA_TIMEOUT;
return(errorstatus);
}
else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
errorstatus = SD_DATA_CRC_FAIL;
return(errorstatus);
}
else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
errorstatus = SD_RX_OVERRUN;
return(errorstatus);
}
else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_STBITERR);
errorstatus = SD_START_BIT_ERR;
return(errorstatus);
}
count = SD_DATATIMEOUT;
while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0))
{
*tempbuff = SDIO_ReadData();
tempbuff++;
count--;
}

/*!< Clear all the static flags */
SDIO_ClearFlag(SDIO_STATIC_FLAGS);

/* Test if the switch mode HS is ok */
if ((hs[13]& 0x2)==0x2)
{
/*!< Configure the SDIO peripheral */
SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
#if defined (STM32F40_41xxx)
SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Falling; /* This is a baddest work around for STM32F40x and STM32F41x */
#else
SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
#endif
SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Enable; /* Set Direct Clock(48MHz) */
SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b;
SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
SDIO_Init(&SDIO_InitStructure);
errorstatus=SD_OK; /* Enter SDHighSpeedMode */
}
else
{
errorstatus=SD_OK; /* Still SDNomalMode */
/*errorstatus=SD_UNSUPPORTED_FEATURE ;*/
}
}
return(errorstatus);
}

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/*!< Configure the SDIO peripheral */
SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
#if defined (STM32F40_41xxx)
SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Falling; /* This is a baddest work around for STM32F40x and STM32F41x */
#else
SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
#endif
SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Enable; /* Set Direct Clock(48MHz) */
SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b;
SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
SDIO_Init(&SDIO_InitStructure);
errorstatus=SD_OK; /* Enter SDHighSpeedMode */

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DRESULT disk_read(uint8_t drv,uint8_t *buff,uint32_t sector,unsigned int count)
{
switch (drv)
{
case SDIO_DRIVE:
{
Status = SD_OK;

if(count==1){
Status = SD_ReadBlock((uint8_t*)(buff),
((uint64_t)(sector)*SECTOR_SIZE),
SECTOR_SIZE);
}
else{
Status = SD_ReadMultiBlocks((uint8_t*)(buff),
((uint64_t)(sector)*SECTOR_SIZE),
SECTOR_SIZE
,count);
}

if (Status == SD_OK) return RES_OK;
else return RES_ERROR;
}
}
return RES_PARERR;
}

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DRESULT disk_write(uint8_t drv,const uint8_t *buff,uint32_t sector,unsigned int count)
{
switch (drv)
{
case SDIO_DRIVE:
{
Status = SD_OK;

if(count==1){
Status = SD_WriteBlock((uint8_t*)(buff),
((uint64_t)(sector)*SECTOR_SIZE),
SECTOR_SIZE);
}
else{
Status = SD_WriteMultiBlocks((uint8_t*)(buff),
((uint64_t)(sector)*SECTOR_SIZE),
SECTOR_SIZE
,count);
}

if (Status == SD_OK) return RES_OK;
else return RES_ERROR;
}
}
return RES_PARERR;
}
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SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize)
{
SD_Error errorstatus = SD_OK;
#if defined (SD_POLLING_MODE)
uint32_t count = 0, *tempbuff = (uint32_t *)readbuff;
#endif

TransferError = SD_OK;
TransferEnd = 0;
StopCondition = 0;

SDIO->DCTRL = 0x0;

#if defined(SD_DMA_MODE)
/* Ready to DMA Before Any SDIO Commands! */
SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize);
SDIO_DMACmd(ENABLE);
#endif

if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
{
BlockSize = 512;
ReadAddr /= 512;
}

/* Set Block Size for Card */
SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
SDIO_SendCommand(&SDIO_CmdInitStructure);

errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);

if (SD_OK != errorstatus)
{
return(errorstatus);
}

SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
SDIO_DataConfig(&SDIO_DataInitStructure);

/*!< Send CMD17 READ_SINGLE_BLOCK */
SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
SDIO_SendCommand(&SDIO_CmdInitStructure);

errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK);

if (errorstatus != SD_OK)
{
return(errorstatus);
}

#if defined (SD_POLLING_MODE)
/*!< In case of single block transfer, no need of stop transfer at all.*/
/*!< Polling mode */
while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
{
if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
{
for (count = 0; count < 8; count++)
{
*(tempbuff + count) = SDIO_ReadData();
}
tempbuff += 8;
}
}

if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
errorstatus = SD_DATA_TIMEOUT;
return(errorstatus);
}
else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
errorstatus = SD_DATA_CRC_FAIL;
return(errorstatus);
}
else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
errorstatus = SD_RX_OVERRUN;
return(errorstatus);
}
else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
{
SDIO_ClearFlag(SDIO_FLAG_STBITERR);
errorstatus = SD_START_BIT_ERR;
return(errorstatus);
}
count = SD_DATATIMEOUT;
while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0))
{
*tempbuff = SDIO_ReadData();
tempbuff++;
count--;
}

/*!< Clear all the static flags */
SDIO_ClearFlag(SDIO_STATIC_FLAGS);

#elif defined(SD_DMA_MODE)
/* Check if the Transfer is finished */
Status = SD_WaitReadOperation();

/* Wait until end of DMA transfer */
while(SD_GetStatus() != SD_TRANSFER_OK);
if (TransferError != SD_OK)
{
return(TransferError);
}
#endif

return(errorstatus);
}

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DSTATUS disk_status(uint8_t drv)
{
switch (drv)
{
case SDIO_DRIVE:
{
Status = SD_GetCardInfo(&SDCardInfo);

if (Status != SD_OK)
return STA_NOINIT;
else
return 0x00;
}
}

return STA_NOINIT;
}

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SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;


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SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4;

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text data bss dec hex filename
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=== Verbose ELF Size ===
text data bss dec hex filename
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Built Object Informations:
=== Total Binary Size ===
text data bss dec hex filename
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=== Verbose ELF Size ===
text data bss dec hex filename
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text data bss dec hex filename
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=== Verbose ELF Size ===
text data bss dec hex filename
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lcd_c_buf_ptr = lcd_f_buf_ptr + 2*(x + (MAX_X*y));

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*(volatile uint16_t*)(lcd_c_buf_ptr) = colour;
lcd_c_buf_ptr +=2;

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/* configure DMA2D */
DMA2D_DeInit();
DMA2D_InitStruct.DMA2D_Mode = DMA2D_R2M;
DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565;
DMA2D_InitStruct.DMA2D_OutputGreen = (0x07E0 & COL_BLACK) >> 5;
DMA2D_InitStruct.DMA2D_OutputBlue = 0x001F & COL_BLACK;
DMA2D_InitStruct.DMA2D_OutputRed = (0xF800 & COL_BLACK) >> 11;
DMA2D_InitStruct.DMA2D_OutputAlpha = 0x0F;
DMA2D_InitStruct.DMA2D_OutputMemoryAdd = (uint32_t)lcd_f_buf_ptr;
DMA2D_InitStruct.DMA2D_OutputOffset = (MAX_X - 1));
DMA2D_InitStruct.DMA2D_NumberOfLine = MAX_X+1;
DMA2D_InitStruct.DMA2D_PixelPerLine = MAX_Y+1;
DMA2D_Init(&DMA2D_InitStruct);
/* Start Transfer */
DMA2D_StartTransfer();
/* Wait for CTC Flag activation */
while(DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET){}


lcd_f_buf_ptr :¥Õ¥ì¡¼¥à¥Ð¥Ã¥Õ¥¡¤È¤·¤Æ³ÎÊݤ·¤¿¥á¥â¥êÎΰè¤Î¥Ù¡¼¥¹¥¢¥É¥ì¥¹
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/* configure DMA2D */
DMA2D_DeInit();
DMA2D_InitStruct.DMA2D_Mode = DMA2D_M2M;
DMA2D_InitStruct.DMA2D_CMode = DMA2D_RGB565;
DMA2D_InitStruct.DMA2D_OutputGreen = 0; /*¡¡M2M·ÏžÁ÷¤Î¾ì¹ç¤Ï»È¤ï¤Ê¤¤ */
DMA2D_InitStruct.DMA2D_OutputBlue = 0; /*¡¡M2M·ÏžÁ÷¤Î¾ì¹ç¤Ï»È¤ï¤Ê¤¤ */
DMA2D_InitStruct.DMA2D_OutputRed = 0; /*¡¡M2M·ÏžÁ÷¤Î¾ì¹ç¤Ï»È¤ï¤Ê¤¤ */
DMA2D_InitStruct.DMA2D_OutputMemoryAdd = (uint32_t)lcd_f_buf_ptr;
DMA2D_InitStruct.DMA2D_OutputOffset = 1;
DMA2D_InitStruct.DMA2D_NumberOfLine = MAX_X+1;
DMA2D_InitStruct.DMA2D_PixelPerLine = MAX_Y+1;
DMA2D_Init(&DMA2D_InitStruct);

/* Configure default values for foreground */
DMA2D_FG_StructInit(&DMA2D_FG_InitStruct);
DMA2D_FG_InitStruct.DMA2D_FGMA = (uint32_t)p;
DMA2D_FGConfig(&DMA2D_FG_InitStruct);

/* Start Transfer */
DMA2D_StartTransfer();
/* Wait for CTC Flag activation */
while(DMA2D_GetFlagStatus(DMA2D_FLAG_TC) == RESET){}


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> "C:¥Devz¥AVR¥WinAVR¥utils¥bin¥make.exe" program
openocd_m0 -s C:/Devz/ARM/OCD/tcl -f target/stm32f0x_stlink_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.6.0-dev-00595-g445a54a-dirty (2012-05-28-09:15)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
1000 kHz
srst_only separate srst_nogate srst_open_drain
Info : clock speed 1000 kHz
Info : stm32f0x.cpu: hardware has 4 breakpoints, 2 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0xc1000000 pc: 0x080007c8 msp: 0x20002000
auto erase enabled
Info : device id = 0x20006440
Info : flash size = 64kbytes
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x2000003e msp: 0x20002000
wrote 3072 bytes from file main.elf in 0.265629s (11.294 KiB/s)
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20002000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20002000
verified 2408 bytes in 0.078126s (30.100 KiB/s)
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0xc1000000 pc: 0x080007c8 msp: 0x20002000
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:



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> "C:¥Devz¥AVR¥WinAVR¥utils¥bin¥make.exe" program
openocd_m0 -s C:/Devz/ARM/OCD/tcl -f interface/vsllink_swd.cfg -f target/stm32f0x_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.6.0-dev-00595-g445a54a-dirty (2012-05-28-09:15)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : OpenOCD runs in SWD mode
1000 kHz
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
cortex_m3 reset_config sysresetreq
verify Capture-IR is disabled
Info : Versaloon(0x15)by Simon(compiled on Feb 29 2012)
Info : USB_TO_XXX abilities: 0x0000076E:0x010001EF:0xC0000007
Info : clock speed 1000 kHz
Info : stm32f1x.cpu: hardware has 4 breakpoints, 2 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0xc1000000 pc: 0x080007c8 msp: 0x20002000
auto erase enabled
Info : device id = 0x20006440
Info : flash size = 64kbytes
wrote 3072 bytes from file main.elf in 0.265628s (11.294 KiB/s)
wrote 2408 bytes from file main.elf in 0.093752s (25.083 KiB/s)
verified 2408 bytes in 0.140626s (16.722 KiB/s)
shutdown command invoked

> Process Exit Code: 0
> Time Taken: 00:



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¤Î¥¿¥Ã¥Á¥»¥ó¥¹¥Ñ¥¿¥ó¤«¤é¤âÆþÎϲÄǽ¤Ç¤¹¡£¥¿¥Ã¥Á¥Ñ¥Í¥ëTFT-LCD¥â¥¸¥å¡¼¥ë¤Î»þ¤È
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> "C:¥Devz¥AVR¥WinAVR¥utils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f target/stm32lx_stlink_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.6.0-dev-00448-gc59a441-dirty (2012-03-01-10:03)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Warn : must select a transport.
1 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
Info : clock speed 1 kHz
Info : IDCODE 2ba01477
Info : stm32lx.cpu: hardware has 6 breakpoints, 4 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0800bf74 msp: 0x20004000
auto erase enabled
Info : flash size = 128kbytes
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x20000012 msp: 0x20004000
wrote 114688 bytes from file main.elf in 12.796548s (8.752 KiB/s)
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x2000003a msp: 0x20004000
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x2000003a msp: 0x20004000
verified 111172 bytes in 0.515612s (210.558 KiB/s)
shutdown command invoked

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> "C:¥Devz¥AVR¥WinAVR¥utils¥bin¥make.exe" program
openocd -s C:/Devz/ARM/OCD/tcl -f interface/vsllink_swd.cfg -f target/stm32lx_swd_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.6.0-dev-00448-gc59a441-dirty (2012-03-01-10:03)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Warn : must select a transport.
Info : OpenOCD runs in SWD mode
100 kHz
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
cortex_m3 reset_config sysresetreq
Info : Versaloon(0x34)by Simon(compiled on Feb 29 2012)
Info : USB_TO_XXX abilities: 0x00000008:0x00000040:0xC0000006
Info : clock speed 100 kHz
Info : stm32l.cpu: hardware has 6 breakpoints, 4 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0800bcb8 msp: 0x20004000
STM32L: Enabling HSI
2000 kHz
auto erase enabled
Info : flash size = 128kbytes
wrote 110592 bytes from file main.elf in 17.983915s (6.005 KiB/s)
verified 110492 bytes in 1.140595s (94.602 KiB/s)
shutdown command invoked

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¤Á¤ç¤Ã¤ÈÈù̯¤Ç¤¹¤Í¡Ä128kByte¤·¤«¤Ê¤¤¤·¤Þ¤¡¤¤¤¤¤Ç¤¹¤«¡£


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"Error: registers may not be the same -- `strexb r0,r0,[r1]"
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uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;

__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}


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uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
register uint32_t result asm ("r2");
register uint8_t value1 asm ("r0") = value;
register volatile uint8_t* addr1 asm ("r1") = addr;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr1), "r" (value1) );
return(result);
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>The two L6928D regulators (U9 and U17) are very sensitive.
>To solve this issue, the patch on U9 is the main measure.
>But it seems not to be sufficent.
>A second measure consists in replacing the input capacitors (C23 and C56)
>by multilayer ceramic capacitors (instead of tantalum).
>We will modify the web page to recommend this additional measure.

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openocd -f C:/Devz/ARM/OCD/daemon.cfg -f C:/Devz/ARM/OCD/tcl/interface/jtagkey.cfg -f C:/Devz/ARM/OCD/tcl/target/stm32_flash.cfg -c "mt_flash main.elf"
Open On-Chip Debugger 0.3.0-in-development (2009-09-03-18:39) svn:2663
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
For bug reports, read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS
1000 kHz
jtag_nsrst_delay: 100
jtag_ntrst_delay: 100
Warn : use 'stm32.cpu' as target identifier, not '0'
Info : device: 4 "2232C"
Info : deviceID: 67358712
Info : SerialNumber: 11111111A
Info : Description: Amontec JTAGkey A
Info : clock speed 1000 kHz
Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: stm32.bs tap/device found: 0x06418041 (mfg: 0x020, part: 0x6418, ver: 0x0)
Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: stm32.bs tap/device found: 0x06418041 (mfg: 0x020, part: 0x6418, ver: 0x0)
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08001b40 msp: 0x2000c000
Info : device id = 0x10016418
Info : flash size = 128kbytes
stm32x mass erase complete
Info : Padding image section 0 with 0 bytes
Warn : not enough working area available(requested 16384, free 16336)
wrote 44704 byte from file main.elf in 2.812626s (15.521527 kb/s)
verified 44704 bytes in 1.125051s
Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: stm32.bs tap/device found: 0x06418041 (mfg: 0x020, part: 0x6418, ver: 0x0)

> Process Exit Code: 0
> Time Taken: 00:05


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Info : JTAG Tap/device matched
Info : JTAG tap: stm32.bs tap/device found: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1)
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